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revision date: mar. 16, 2004 8 h8/3802, h8/38004, h8/38104 group hardware manual renesas 8-bit single-chip microcomputer h8 family / h8/300l super low power series rev. 4.00 rej09b0024-0400o
rev. 4.00, 03/04, page ii of l 1. these materials are intended as a reference to assist our customers in the selection of the renesas technology corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to renesas technology corp. or a third party. 2. renesas technology corp. assumes no responsibility for any damage, or infringement of any third- party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by renesas technology corp. without notice due to product improvements or other reasons. it is therefore recommended that customers contact renesas technology corp. or an authorized renesas technology corp. product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. renesas technology corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by renesas technology corp. by various means, including the renesas technology corp. semiconductor home page (http://www.renesas.com). 4. when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. renesas technology corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. renesas technology corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact renesas technology corp. or an authorized renesas technology corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. the prior written approval of renesas technology corp. is necessary to reprint or reproduce in whole or in part these materials. 7. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a license from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. 8. please contact renesas technology corp. for further details on these materials or the products contained therein. 1. renesas technology corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. keep safety first in your circuit designs! notes regarding these materials
rev. 4.00, 03/04, page iii of l general precautions on handling of product 1. treatment of nc pins note: do not connect anything to the nc pins. the nc (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. if something is connected to the nc pins, the operation of the lsi is not guaranteed. 2. treatment of unused input pins note: fix all unused input pins to high or low level. generally, the input pins of cmos products are high-impedance input pins. if unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a pass- through current flows internally, and a malfunction may occur. 3. processing before initialization note: when power is first supplied, the product?s state is undefined. the states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. during the period where the states are undefined, the register settings and the output state of each pin are also undefined. design your system so that it does not malfunction because of processing while it is in this undefined state. for those products which have a reset function, reset the lsi immediately after the power supply has been turned on. 4. prohibition of access to undefined or reserved addresses note: access to undefined or reserved addresses is prohibited. the undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresses. do not access these registers; the system?s operation is not guaranteed if they are accessed.
rev. 4.00, 03/04, page iv of l configuration of this manual this manual comprises the following items: 1. general precautions on handling of product 2. configuration of this manual 3. preface 4. contents 5. overview 6. description of functional modules cpu and system-control modules on-chip peripheral modules the configuration of the functional description of each module differs according to the module. however, the generic style includes the following items: i) feature ii) input/output pin iii) register description iv) operation v) usage note when designing an application system that includes this lsi, take notes into account. each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section. 7. list of registers 8. electrical characteristics 9. appendix 10. main revisions and additions in this edition (only for revised versions) the list of revisions is a summary of points that have been revised or added to earlier versions. this does not include all of the revised contents. for details, see the actual locations in this manual. 11. index
rev. 4.00, 03/04, page v of l preface the h8/3802 group, h8/38004 group, and h8/38104 group are single-chip microcomputers made up of the high-speed h8/300l cpu employing renesas technology?s original architecture as their cores, and the peripheral functions required to configure a system. the h8/300l cpu has an instruction set that is compatible with the h8/300 cpu. below is a table listing the product specifications for each group. 3802 38004 38104 item ztat mask rom flash mask rom flash mask rom memory rom 32k 8kto32k 16k/32k 8kto32k 32k 8kto32k ram 1 k 512 or 1 k 1 k 512 or 1 k 1 k 512 or 1 k 4.5to5.5v 16mhz 16mhz ? ? 16mhz 16mhz 2.7to5.5v 10mhz 10mhz ? ? 16mhz 16mhz 1.8to5.5v 4mhz4mhz???? 2.7to3.6v ? ? 10mhz 10mhz ? ? operating voltage and operating frequency 1.8to3.6v ? ? 4mhz(2.2v or more) 4mhz ? ? i/oportsinput 999999 output 666655 i/o 515151515151 timersclock(timera) 111111 compare(timerf) 111111 aec 111111 wdt 1111 wdt (discrete) 11 sci uart/clock frequency 1 ch 1 ch 1 ch 1 ch 1 ch 1 ch a-d 10 410 410 410 410 410 4 lcd seg 25 25 25 25 25 25 com 444444 external interrupt (internal wakeup) 11(8) 11(8) 11(8) 11(8) 11(8) 11(8) por(power-onreset) ???? 1 ? lvd ???? 1 ? package fp-64a fp-64a fp-64a fp-64a fp-64a fp-64a fp-64e fp-64e fp-64e fp-64e fp-64e fp-64e dp-64s dp-64s die die die operating temperature standard specifications: ?20 to 70 c, wtr: ?40 to 85 c
rev. 4.00, 03/04, page vi of l target users: this manual was written for users who will be using the h8/3802 group, h8/38004 group, and h8/38104 group in the design of application systems. target users are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers. objective: this manual was written to explain the hardware functions and electrical characteristics of the h8/3802 group, h8/38004 group, and h8/38104 group to the target users. refer to the h8/300l series programming manual for a detailed description of the instruction set. notes on reading this manual: ? in order to understand the overall functions of the chip read the manual according to the contents. this manual can be roughly categorized into parts on the cpu, system control functions, peripheral functions and electrical characteristics. ? in order to understand the details of the cpu's functions read the h8/300l series programming manual. ? in order to understand the details of a register when its name is known read the index that is the final part of the manual to find the page number of the entry on the register. the addresses, bits, and initial values of the registers are summarized in section 14, list of registers. example: bit order: the msb is on the left and the lsb is on the right. notes: the following limitations apply to h8/38004, h8/38002, h8/38104, and h8/38102 programming and debugging when the on-chip emulator is used. 1. pin p95 is not available because it is used exclusively by the on-chip emulator. 2. pins p33, p34, and p35 are unavailable for use. in order to use these pins additional hardware must be mounted on the user board. 3. the address range h'7000 to h'7fff is used by the on-chip emulator and is unavailable to the user. 4. the address range h'f780 to h'fb7f must not be accessed under any circumstances. 5. when the on-chip emulator is being used, pin p95 is i/o, pins p33 and p34 are input, and pin p35 is output. 6. when using the on-chip emulator, pins osc1 and osc2 should be connected to an oscillator, or an external clock should be supplied to pin osc1, even if the on-chip oscillator of the h8/38104 group is selected. related manuals: the latest versions of all related manuals are available from our web site. please ensure you have the latest versions of all documents you require. http://www.renesas.com/eng/
rev. 4.00, 03/04, page vii of l h8/3802 group and h8/38004 group manuals: document title document no. h8/3802 group, h8/38004 group, h8/38104 group hardware manual this manual h8/300l series programming manual ade-602-040 user's manuals for development tools: document title document no. h8s, h8/300 series c/c++ compiler, assembler, optimizing linkage editor user's manual rej10b0058-0100h (ade-702-247) h8s, h8/300 series simulator/debugger user's manual ade-702-282 h8s, h8/300 series high-performance embedded workshop, high- performance debugging interface tutorial ade-702-231 high-performance embedded workshop user's manual ade-702-201 application notes: document title document no. single power supply f-ztat tm on-board programming ade-502-055
rev. 4.00, 03/04, page viii of l
rev. 4.00, 03/04, page ix of l main revisions and additions in this edition item page revisions (see manual for details) all h8/38104 group added preface vii 3802 38004 38104 item ztat mask rom flash mask rom flash mask rom i/o ports input 9 9 9 9 9 9 output 6666 5 i/o 51 51 51 51 51 51 5 viii note 6 and specifications added 6. when using the on-chip emulator, pins osc1 and osc2 should be connected to an oscillator, or an external clock should be supplied to pin osc1, even if the on-chip oscillator of the h8/38124 group is selected. 1.1 features 1 description amended complete instruction set compatibility with h8/300 cpu watchdog timer (wdt) (h8/38004 group and h8/38104 group only) power-on reset and low-voltage detect circuits (h8/38104 group only) 2 on-chip memory h8/38104 hd64f38104 32 kbytes 1 kbyte h8/38102 hd64f38102 16 kbytes 1 kbyte h8/38104 hd64338104 32 kbytes 1 kbyte h8/38103 hd64338103 24 kbytes 1 kbyte h8/38102 hd64338102 16 kbytes 1 kbyte h8/38101 hd64338101 12 kbytes 512 bytes h8/38100 hd64338100 8 kbytes 512 bytes general i/o ports output-only pins: 6 output pins (5 pins on h8/38104 group) 3 compact package the chip is not supported by the h8/38104 group . 1.2 internal block diagram figure 1.3 internal block diagram of h8/38104 group 6 newly added
rev. 4.00, 03/04, page x of l item page revisions (see manual for details) 1.3 pin arrangement figure 1.6 pin arrangement of h8/38104 group (fp-64a, fp-64e) 9 newly added figure 1.9 pad arrangement of hcd64f38004 and hcd64f38002 (top view) 16 figure 1.9: table amended hcd64f38004 hcd64f38004c4 hcd64f38002 hcd64f38002c4 hd64f38004 product model name model name on chip hd64f38004-4 hd64f38004 hd64f38004-4 1.4 pin functions 19 to 22 table amended and notes amended power source pins cv cc * 4 53 ? ? ? input this is the internal step-down power supply pin. to ensure stability, a capacitor with a rating of about 0.1 f should be connected between this pin and the v ss pin. interrupt pins irqaec 56 64 57 56 input asynchronous event counter interrupt input pin. enables asynchronous event input. on the h8/38104 group, this must be fixed at v cc or gnd because the oscillator is selected by the input level during resets . refer to section 4, clock pulse generators, for information on the selection method. i/o ports p95 to p90 54 to 49 62 to 57 55 to 50 54 to 49 output 6-bit output port. when the on-chip emulator is used, pin p95 is unavailable to the user because it is used exclusively by the on-chip emulator. in the f-ztat version, pin p95 should not be open but pulled up to go high in user mode. note that the h8/38104 group is not equipped with a pin 94. vref 52 ? ? ? input reference voltage input pin. extd 62 ? ? ? input power supply drop detection voltage input pin. low- voltage detection circuit (lvd) * 4 extu 63 ? ? ? input power supply rise detection voltage input pin. note: 4. h8/38104 group only
rev. 4.00, 03/04, page xi of l item page revisions (see manual for details) 2.2 address space and memory map figure 2.1(4) h8/38004 , h8/38104 memory map figure 2.1(5) h8/38003 , h8/38103 memory map figure 2.1(6) h8/38002 , h8/38102 memory map figure 2.1(7) h8/38001 , h8/38101 memory map figure 2.1(8) h8/38000 , h8/38100 memory map 27 to 31 title amended 65 table amended p37 p36 p35 p34 p33 p32 p31 ? ? ? ? input/output input input output output output output output ? 2.9.4 bit manipulation instructions example 2: after executing bset pin state low level high level low level low level low level low level high level ? pcr3 0 0 1 1 1 1 1 1 pdr3 1 0 0 0 0 0 1 1 ram0 100000 11 section 3 exception handling 69, 70 note on hd64f38004 added 71 table amended and note added irq0 /low-voltage detect interrupt * 4 h'0008toh'0009 irq1 5 h'000a to h'000b external interrupt pin/ low-voltage detect circuit (lvd) * irqaec 6 h'000c to h'000d 3.1 exception sources and vector address table 3.1 exception sources and vector address note: * the low-voltage detection circuit and low-voltage detection interrupt are implemented on the h8/38104 group only.
rev. 4.00, 03/04, page xii of l item page revisions (see manual for details) 3.3 reset exception handling 78 description added when the res pin goes low, all processing halts and this lsi enters the reset. the internal state of the cpu and the registers of the on-chip peripheral modules are initialized by the reset. to ensure that this lsi is reset at power-on, hold the res pin low until the clock pulse generator output stabilizes. to reset the chip during operation, hold the res pin low for at least 10 system clock cycles. when the res pin goes high after being held low for the necessary time, this lsi starts reset exception handling. the reset exception handling sequence is shown in figure 3.1. the reset exception handling sequence is as follows. however, refer to section 14.3.1, power-on reset circuit, for information on the reset sequence for the h8/38104 group, which has a built-in power-on reset function. 84 table amended iwpr iwpf7 when pmr5 bit wkp7 is changed from 0 to 1 while pin wkp7 is low and wegr bit wkegs7 = 0. when pmr5 bit wkp7 is changed from 1 to 0 while pin wkp7 is low and wegr bit wkegs7 = 1. iwpf6 when pmr5 bit wkp6 is changed from 0 to 1 while pin wkp6 is low and wegr bit wkegs6 = 0. when pmr5 bit wkp6 is changed from 1 to 0 while pin wkp6 is low and wegr bit wkegs6 = 1. 3.5.3 notes on rewriting port mode registers table 3.3 conditions under which interrupt request flag is set to 1 iwpf5 when pmr5 bit wkp5 is changed from 0 to 1 while pin wkp5 is low and wegr bit wkegs5 = 0. when pmr5 bit wkp5 is changed from 1 to 0 while pin wkp5 is low and wegr bit wkegs5 = 1. iwpf4 when pmr5 bit wkp4 is changed from 0 to 1 while pin wkp4 is low and wegr bit wkegs4 = 0. when pmr5 bit wkp4 is changed from 1 to 0 while pin wkp4 is low and wegr bit wkegs4 = 1. iwpf3 when pmr5 bit wkp3 is changed from 0 to 1 while pin wkp3 is low and wegr bit wkegs3 = 0. when pmr5 bit wkp3 is changed from 1 to 0 while pin wkp3 is low and wegr bit wkegs3 = 1. iwpf2 when pmr5 bit wkp2 is changed from 0 to 1 while pin wkp2 is low and wegr bit wkegs2 = 0. when pmr5 bit wkp2 is changed from 1 to 0 while pin wkp2 is low and wegr bit wkegs2 = 1. iwpf1 when pmr5 bit wkp1 is changed from 0 to 1 while pin wkp1 is low and wegr bit wkegs1 = 0. when pmr5 bit wkp1 is changed from 1 to 0 while pin wkp1 is low and wegr bit wkegs1 = 1. iwpf0 when pmr5 bit wkp0 is changed from 0 to 1 while pin wkp0 is low and wegr bit wkegs0 = 0. when pmr5 bit wkp0 is changed from 1 to 0 while pin wkp0 is low and wegr bit wkegs0 = 1.
rev. 4.00, 03/04, page xiii of l item page revisions (see manual for details) 4.1 features figure 4.1 block diagram of clock pulse generators (h8/3802, h8/38004 group) figure 4.2 block diagram of clock pulse generators (h8/38104 group) 87 description added clock oscillator circuitry (cpg: clock pulse generator) is provided on- chip, including both a system clock pulse generator and a subclock pulse generator. in the h8/38104 group, the system clock pulse generator includes an on-chip oscillator. the system clock pulse generator consists of a system clock oscillator and system clock dividers. the subclock pulse generator consists of a subclock oscillator and a subclock divider. figure 4.1 shows a block diagram of the clock pulse generators of the h8/3802 and h8/38004 group. figure 4.2 shows a block diagram of the clock pulse generators of the h8/38104 group. figure 4.1: title amended figure 4.2: newly added 4.2 register description 89 newly added 4.3 system clock generator 90 description added as shown in figure 4.2, the h8/38104 group supports selection between a system clock oscillator and an on-chip oscillator. see section 4.3.4, on-chip oscillator selection method, for information on selecting the on- chip oscillator. 90, 91 description amended figure 4.4(1) shows a typical method of connecting a crystal oscillator to the h8/3802 group, and figure 4.4(2) shows a typical method of connecting a crystal oscillator to the h8/38004 and h8/38104 group. figure 4.4(1): title amended figure 4.4(2): newly added table 4.1: table amended frequency (mhz) 4.10 4.193 4.3.1 connecting crystal resonator figure 4.4(1) typical connection to crystal resonator (h8/3802 group) figure 4.4(2) typical connection to crystal resonator (h8/3804, h8/38104 group) r s (max) 100 ? c 0 (max) 16 pf 4.3.2 connecting ceramic resonator figure 4.6(1) typical connection to ceramic resonator (h8/3802 group) figure 4.6(2) typical connection to ceramic resonator (h8/38004, h8/38104 group) 91, 92 description amdended figure 4.6(1) shows a typical method of connecting a ceramic oscillator to the h8/3802 group, and figure 4.6(2) shows a typical method of connecting a crystal oscillator to the h8/38004 and h8/38104 group. figure 4.6(1): title amended figure 4.6(2): newly added.
rev. 4.00, 03/04, page xiv of l item page revisions (see manual for details) 4.3.4 on-chip oscillator selection method (h8/38104 group only) 92 newly added 4.4 subclock generator 93 description added figure 4.8 shows a block diagram of the subclock generator. note that on the h8/38104 group the subclock oscillator can be disabled by programs by setting the substp bit in the osccr register. the register setting to disable the subclock oscillator should be made in the active mode. when restoring operation of the subclock oscillator after it has been disabled using the osccr register, it is necessary to wait for the oscillation stabilization time ( typ = 8s) to elapse before using the subclock . 4.4.1 connecting 32.768-khz/38.4-khz crystal resonator 93 description added clock pulses can be supplied to the subclock divider by connecting a 32.768-khz or 38.4-khz crystal resonator, as shown in figure 4.9. figure 4.10 shows the equivalent circuit of the 32.768-khz or 38.4-khz crystal resonator. note that only operation at 32.768 khz is guaranteed on the h8/38104 group. 4.4.3 external clock input 94 description added connect the external clock to pin x1 and leave pin x2 open, as shown in figure 4.12. note that input of an external clock is not supported on the h8/38104 group. 4.6.4 notes on use of crystal resonator (excluding ceramic resonator) 100 description and note added for example, if erroneous operation occurs with a standby time setting of 16 states, check the operation with a standby time setting of 1,024 * states or more. if the same kind of erroneous operation occurs after a reset as after a state transition, hold the res pin low for a longer period. note: * this figure applies to the h8/3802 and h8/38004 groups. the number of states on the h8/38104 group is 8,192 or more. 4.6.5 notes on h8/38104 group 100 newly added
rev. 4.00, 03/04, page xv of l item page revisions (see manual for details) 102 bit table amended 5.1.1 system control register 1(syscr1) 6 5 4 sts2 sts1 sts0 0 0 0 r/w r/w r/w standby timer select 2 to 0 designate the time the cpu and peripheral modules wait for stable clock operation after exiting from standby mode, subactive mode, subsleep mode, or watch mode to active mode or sleep mode due to an interrupt. the designation should be made according to the operating frequency so that the waiting time is at least equal to the oscillation stabilization time. the relationship between the specified value and the number of wait states is shown in tables 5.1(1) and 5.1(2). when an external clock is to be used, the minimum value (sts2 = 1, sts1 = 0, sts0 = 1) is recommended. 8,192 states (sts2 = sts1 = sts0 = 0) is recommended if the on-chip oscillator is used on the h8/38104 group. if the setting other than the recommended value is made, operation may start before the end of the waiting time. table 5.1(1) operating frequency and waiting time (h8/3802 group, h8/38004 group) table 5.1(2) operating frequency and waiting time (h8/38104 group) 103, 104 table 5.1(1): title amended table 5.1(2): newly added note amended when the on-chip clock oscillator is used on the h8/38104 group, a setting of 8,192 states (sts2 = sts1 = sts0 = 0) is recommended. 105 bit table amended 5.1.3 clock halt registers 1 and 2 (ckstpr1 and ckstpr2) ckstpr2 7 lvdckstp 1 r/w lvd module standby the lvd module enters standby status when this bit is cleared to 0. note: on products other than the h8/38104 group, this bit is reserved like bits 6 and 5. 6, 5 ? all 1 ? reserved
rev. 4.00, 03/04, page xvi of l item page revisions (see manual for details) table amended, notes amended 109, 110 wdt function- ing/ reta - ined * 9 function- ing/reta- ined * 8 function- ing/ reta - ined * 9 function ing/ reta - ined * 10 5.2 mode transitions and states of lsi table 5.3 internal state in each operating mode lvd func- tioning func- tioning func- tioning func- tioning func- tioning func- tioning func- tioning func- tioning notes: 8. on the h8/38104 group, operates when w/32 is selected as the internal clock or the on-chip oscillator is selected; otherwise stops and stands by. on the h8/38004 group, operates when w/32 is selected as the internal clock; otherwise stops and stands by. 9. on the h8/38104 group, operates when w/32 is selected as the internal clock or the on-chip oscillator is selected; otherwise stops and stands by. on the h8/38004 group, stops and stands by. 10. on the h8/38104 group, operates only when the on-chip oscillator is selected; otherwise stops and stands by. on the h8/38004 group, stops and stands by. section 6 rom 119 description amended the h8/3802 has 16 kbytes of the on-chip mask rom, the h8/3801 has 12 kbytes, and the h8/3800 has 8 kbytes. the h8/38004 and h8/38104 have 32 kbytes of the on-chip mask rom, the h8/38003 and h8/38103 have 24 kbytes, the h8/38002 and h8/38102 have 16 kbytes, the h8/38001 and h8/38101 have 12 kbytes, and the h8/38000 and h8/38100 have 8 kbytes. the rom is connected to the cpu by a 16-bit data bus, allowing high-speed two-state access for both byte data and word data. the h8/3802 has a ztat version with 16-kbyte prom. the h8/38004, h8/38002, h8/38104, and h8/38102 have f-ztat? versions with 32-kbyte flash memory and 16-kbyte flash memory, respectively. 6.5.1 features 129 description amended, note added programming/erase methods ? the flash memory is programmed 128 bytes at a time. erase is performed in single-block units. the flash memory of the hd64f38004 and hd64f38104 are configured as follows: 1 kbyte 4 blocks and 28 kbytes 1 block. the flash memory of the hd64f38002 and hd64f38102 are configured as follows: 1 kbyte 4 blocks and 12 kbytes 1 block. to erase the entire flash memory, each block must be erased in turn. note: the system clock oscillator must be used when programming or erasing the flash memory of the hd64f38104, hd64f38102.
rev. 4.00, 03/04, page xvii of l item page revisions (see manual for details) 134 bit table amended 6.6.3 erase block register (ebr) bit bit name initial value r/w description 4 eb4 0 r/w when this bit is set to 1, 28 kbytes of h'1000 to h'7fff will be erased in the hd64f38004 and hd64f38104. when this bit is set to 1, 12 kbytes of h'1000 to h'3fff will be erased in the hd64f38002 and hd64f38102. 139 table amended product group host bit rate oscillation frequency range of lsi (f osc ) 4,800 bps 8 to 10 mhz 2,400 bps 4 to 10 mhz h8/38004f group 1,200 bps 2 to 10 mhz 6.7.1 boot mode table 6.7 oscillation frequencies for which automatic adjustment of sli bit rate is possible (f osc ) h8/38104f group 19,200 bps 16 mhz 9,600 bps 8to16mhz 4,800 bps 4to16mhz 2,400 bps 2to16mhz 1,200 bps 2to16mhz 6.7.3 notes on on- board programming 140 newly added 6.8.1 program/ program-verify figure 6.10 program/program- verify flowchart 142 figure amended no yes verify data = write data? n 6.8.3 interrupt handling when programming/erasing flash memory figure 6.11 erase/ erase-verify flowchart 145 figure amended ye s no verify data = all 1s ? esu bit
rev. 4.00, 03/04, page xviii of l item page revisions (see manual for details) 6.10.1 socket adapter 147 description amended the socket adapter converts the pin allocation of the hd64f38004, hd64f38002, hd64f38104, and hd64f38102 to that of the discrete flash memory hn28f101. the address of the on-chip flash memory is h'0000 to h'7fff. figure 6.12(1) shows a socket-adapter-pin correspondence diagram of the hd64f38004 and hd64f38002. figure 6.12(2) shows a socket-adapter-pin correspondence of the hd64f38104 and hd64f38102. 6.10.2 programmer mode commands figure 6.12(1) socket adapter pin correspondence diagram (h8/38004f, h8/38002f) figure 6.12(2) socket adapter pin correspondence diagram (h8/38104f, h8/38102f) 148, 149 figure 6.12(1) title amended figure 6.12(2) newly added section 7 ram 161 table amended h8/38004 1 kbyte h'fb80 to h'ff7f flash memory version h8/38002 1 kbyte h'fb80 to h'ff7f h8/38104 1 kbyte h'fb80 to h'ff7f h8/38102 1 kbyte h'fb80 to h'ff7f h8/38104 1 kbyte h'fb80 to h'ff7f mask rom version h8/38103 1 kbyte h'fb80 to h'ff7f h8/38102 1 kbyte h'fb80 to h'ff7f h8/38101 512 bytes h'fd80 to h'ff7f h8/38100 512 bytes h'fd80 to h'ff7f
rev. 4.00, 03/04, page xix of l item page revisions (see manual for details) 164 table and notes amended section 8 i/o ports table 8.1 port functions port 9 p95top92 (p95, p92, p93/vref) * 3 none (lvd reference voltage external input pin) * 3 (lvdsr) * 3 6-bitoutput- only port high-voltage, large-current port * 2 p91, p90/ pwm2, pwm1 10-bit pwm output pmr9 high-voltage, input port * 4 irqaec none port b 4-bit input- only port pb3/an3/ irq1 a/d converter analog input external interrupt 1 amr pmrb pb2/an2 a/d converter analog input amr pb1/an1/ ( extu ) * 5 pb0/an0/ ( extd ) * 5 a/d converter analog input (lvd detection voltage external input pin) * 5 amr (lvdcr) * 5 notes: 1. implemented on h8/3802 group a nd h8/38104 group only. 2. implemented on h8/3802 group only. standard high-voltage port on h8/38104 group and h8/38004 group. 3. implemented on h8/38104 group only. pin 94 does not function on h8/38104 group. 4. implemented on h8/3802 group only. input port on h8/38004 group and h8/38104 group. 5. implemented on h8/38104 group only. 169 table and note added 8.1.5 port mode register 2 (pmr2) 2 wdcks 0 r/w watchdog timer source clock select this bit selects the input clock for the watchdog timer. note that this bit is implemented differently on the h8/38004 group and on h8/38104 group. h8/38004 group: 0: /8,192 1: w/32 h8/38104 group: 0: clock specified by timer mode register w (tmw) 1: w/32 note: this bit is reserved and only 0 can be written in the h8/3802 group. note: * see section 9.5, watchdog timer, for details.
rev. 4.00, 03/04, page xx of l item page revisions (see manual for details) 8.7 port 9 figure 8.8 port 9 pin configuration 188 figure amended p95 p94 * 1 p93/vref * 2 p92 p91/pwm2 p90/pwm1 port 9 notes: 1. there is no pin 94, and its function is not implemented, on the h8/38104 group. 2. the vref pin is implemented on the h8/38104 group only. 188 table amended 8.7.1 port data register 9 (pdr9) bit bit name initial value r/w description 7, 6 ? all 1 ? reserved the initial value should not be changed. 5 4 3 2 1 0 p95 p94 * p93 p92 p91 p90 1 1 1 1 1 1 r/w r/w r/w r/w r/w r/w if pdr9 is read, the values stored in pdr9 are read. note: * there is no pin 94, and its function is not implemented, on the h8/38104 group. however, the register is read/write enabled. 189 bit 3 amended 8.7.2 port mode register 9 (pdm9) 3 pioff 0 r/w p92top90step-upcircuitcontrol this bit turns on and off the p92 to p90 step-up circuit. 0: step-up circuit of large-current port is turned on 1: step-up circuit of large-current port is turned off note: this is a readable/writable reserved bit in the h8/38004 group and h8/38104 group. 8.7.3 pin functions 190 p93/vref added p93/vref as shown below, switching is performed based on the setting of vcss in lvdsr. note that this function is implemented on the h8/38104 group only. the v ref pin is the input pin for the lvd?s external reference voltage. vcss1 0 1 pin function p93 output pin vref input pin
rev. 4.00, 03/04, page xxi of l item page revisions (see manual for details) 8.9 port b figure 8.10 port b pin configuration 192 figure amended, note added pb3/an3/ irq1 pb2/an2 pb1/an1/extu * pb0/an0/extd * port b note: * the extu and extd pins are implemented on the h8/38104 group only. 8.9.3 pin functions 194 bit table amended pb1/an1extu pb1/an1/ extu pin switching is accomplished by combining ch3 to ch0 in amr and vintusel in lvdcr as shown below. note that the extu pin and vintusel are implemented on the h8/38104 group only. vintusel 0 1 ch3 to ch0 other than b 0101 b'0101 * pin function pb1 input pin an1 input pin extu input pin [legend] * : don't care pb0/and/extd pb0/an0/ extd pin switching is accomplished by combining ch3 to ch0 in amr and vintdsel in lvdcr as shown below. note that the extd pin and vintdsel are implemented on the h8/38104 group only. vintdsel 0 1 ch3 to ch0 other than b 0100 b'0100 * pin function pb0 input pin an0 input pin extd input pin [legend] * : don't care
rev. 4.00, 03/04, page xxii of l item page revisions (see manual for details) 9.1 overview 197 description amended the h8/3802 group provides three timers: timer a, timer f, and asynchronous event counter. the h8/38004 group and h8/38104 group provide four timers: timer a, timer f, asynchronous event counter, and watchdog timer. 198 table amended, note added table 9.1 timer functions watchdog timer * /8192, w /32 ?? h8/38004 group generates a reset signal by overflow of 8-bit counter /64 to /8192 w/32 on-chip oscillator h8/38104 group note: * the watchdog timer functions differently on the h8/38004 and h8/38104 group. see section 9.5, watchdog timer, for details. 225 table amended bit bit name initial value r/w description 9.4.3 register descriptions event counter control/status register (eccsr): 6ovl 0 r/w * counter overflow l this is a status flag indicating that ecl has overflowed. [setting condition] when ecl overflows from h'ff to h'00 [clearing condition] when this bit is written to 0 after reading ovl = 1 9.4.4 operation irqaec operation: 229 note added note: on the h8/38104 group, control of switching between the system clock oscillator and the on-chip oscillator during resets should be performed by setting the irqaec input level. refer to section 4.4, subclock generator, for details. 9.5 watchdog timer 234 description amended however, as shown in watchdog timer block diagrams figure 9.12 (1) and figure 9.12 (2), the implementation differs in the h8/38004 group and the h8/38104 group.
rev. 4.00, 03/04, page xxiii of l item page revisions (see manual for details) 9.5.1 features 234 description added selectable from two counter input clocks (h8/38004 group). two clock sources ( /8192 or w /32) can be selected as the timer- counter clock. on the h8/38104 group, 10 internal clocks are available for selection. ten internal clocks ( /64, /128, /256, /512, /1024, /2048, /4096, /8192, w/32, or on-chip oscillator) can be selected as the timer- counter clock. figure 9.12(1) block diagram of watchdog time (h8/38004 group) figure 9.12(2) block diagram of watchdog time (h8/38104 group) 234, 235 figure 9.12(1) title amended figure 9.12(2) newly added 9.5.2 register descriptions 235 description added timer mode register w (tmw) * note: * this register is implemented on the h8/38104 group only. 236, 237 timer control/status register w (tcsrw) table and notes added timer control/status register w (tcsrw) 2wdon 0/1 * 2 r/(w) * 1 watchdog timer on tcw starts counting up when wdon is set to 1 and halts when wdon is cleared to 0. [setting condition] when1iswrittentothewdonbit while writing 0 to the b2wi bit when the tcsrwe bit=1 [clearing condition] reset by res pin * 3 when0iswrittentothewdonbit while writing 0 to the b2wi when the tcsrwe bit=1 notes: 2. initial value 0 on h8/38004 group and 1 on h8/38104 group. 3. on reset, cleared to 0 on h8/38004 group and set to 1 on h8/38104 group. timer mode register w (tmw) 237 timer mode register w (tmw) newly added
rev. 4.00, 03/04, page xxiv of l item page revisions (see manual for details) 9.5.3 operation 238 description added the watchdog timer is provided with an 8-bit counter. the input clock is selected by the wdcks bit in the port mode register 2 (pmr2) * : on the h8/38004 group, /8192 is selected when the wdcks bit is cleared to 0, and w/32 when set to 1. on the h8/38104 group, the clock specified by timer mode register w (tmw) is selected when wdcks is cleared to 0, and w/32 is selected when wdcks is set to 1. if 1 is written to wdon while writing 0 to b2wi when the tcsrwe bit in tcsrw is set to 1, tcw begins counting up. (to operate the watchdog timer, two write accesses to tcsrw are required. however, on the h8/38104 group, tcw begins counting up even if no write access occurs, because wdon is set to 1 when the reset is cleared.) when a clock pulse is input after the tcw count value has reached h'ff, the watchdog timer overflows and an internal reset signal is generated. 9.5.4 operating states of watchdog timer 239 description amended tables 9.8 (1) and 9.8(2) summarize the operating states of the watchdog timer for the h8/38004 group and h8/38104 group, respectively. table 9.8 (1) operating states of watchdog timer (h8/38004 group) table 9.8(2) operating states of watchdog timer (h8/38104 group) table added 10.1 features 241 note added note: on the h8/38104 group, the system clock generator must be used when carrying out this function. 10.3.8 bit rate register (brr) 250 description deleted error (%) =
rev. 4.00, 03/04, page xxv of l item page revisions (see manual for details) 10.3.8 bit rate register (brr) table 10.2 examples of brr settings for various bit rates (asynchronous mode)(1) table 10.2 examples of brr settings for various bit rates (asynchronous mode)(2) 251, 252 table amended osc 32.8 khz 38.4 khz 2 mhz 2.4576 mhz bit rate (bit/s )nn error (%) n n error (%) n n error (%) n n error (%) 110 ?? ? ?? ? 217 ? 1.36 2 21 ? 0.83 150 ?? ? 0 3 0 2 12 0.16 3 3 0 200 ?? ? 02 0 29 ? 2.34 3 2 0 250 0 1 2.5 ?? ? 31 ? 2.34 0 153 ? 0.26 300 ?? ? 0 1 0 0 103 0.16 3 1 0 600 ?? ? 0 0 0 0 51 0.16 3 0 0 1200 ?? 0 25 0.16 2 1 0 2400 12 0.16 2 0 0 4800 ?? ? ? 0 ? 07 0 9600 ?? 03 0 19200 ?? ? 01 0 31250 0 0 0 ?? ? 38400 ?? ? 00 0 osc 4 mhz 10 mhz 16 mhz bit rate (bit/s) nn error (%) n n error (%) n n error (%) 110 3 8 ?1.36 3 21 0.88 3 35 ?1.36 150 2 25 0.16 3 15 1.73 3 25 0.16 200 3 4 ?2.34 3 11 1.73 3 19 ?2.34 250 2 15 ?2.34 3 9 ?2.34 3 15 ?2.34 300 2 12 0.16 3 7 1.73 3 12 0.16 600 0 103 0.16 3 3 1.73 2 25 0.16 1200 0 51 0.16 3 1 1.73 2 12 0.16 2400 0 25 0.16 3 0 1.73 0 103 0.16 4800 0 12 0.16 2 1 1.73 0 51 0.16 9600 ? ? ? 2 0 1.73 0 25 0.16 19200 ? ? ? 0 7 1.73 0 12 0.16 31250 0 1 0 0 4 0 0 7 0 38400 ? ? ? 0 3 1.73 ? ? ? legend no indication: setting not possible. ? : a setting is available but error occurs 10.6.2 multiprocessor serial data reception figure 10.17 sample multiprocessor serial reception flowchart (1) 277 figure amended yes no no yes fer+oer = 1 rdrf = 1 set mpie bit in scr3 to 1 [1] [2] read oer and fer flags in ssr read rdrf flag in ssr [3]
rev. 4.00, 03/04, page xxvi of l item page revisions (see manual for details) 10.8.10 oscillator use with serial communications interface 3 (h8/38104 group only) 286 newly added section 11 10-bit pwm 287 description amended this lsi has a two-channel 10-bit pwm. the pwm with a low-path filter connected can be used as a d/a converter. figure 11.1(1) shows a block diagram of the 10-bit pwm of the h8/3802 group and h8/38004 group. figure 11.1(2) shows a block diagram of the 10-bit pwm of the h8/38104 group. 11.1 features figure 11.1(1) block diagram of 10-bit pwm (h8/3802 group, h8/38004 group) figure 11.1(2) block diagram of 10-bit pwm (h8/38104 group) 287, 288 description added on the h8/38104 group it is possible to select between two types of pwm output: pulse-division pwm and event counter pwm (pwm incorporating aec). (the h8/3802 group and h8/38004 group can only produce 10-bit pwm output.) refer to section 9.4, asynchronous event counter, for information on event counter pwm. figure 11.1(1) title amended figure 11.1(2) newly added 288 table amended name abbreviation i/o function 11.2 input/output pins table 11.1 pin configuration 10-bit pwm square-wave output 1 pwm1 output channel 1: 10-bit pwm waveform output pin/ event counter pwm output pin * 10-bit pwm square-wave output 2 pwm2 output channel 2: 10-bit pwm waveform output pin/ event counter pwm output pin * note: * h8/38104 group only 11.3.1 pwm control register (pwcr) 289, 290 description amended on the h8/3802 group and h8/38004 group, pwcr selects the conversion period. bit descriptions for h8/38104 group newly added 11.4.1 operation 291 description amended 2. set the pwcr0 and pwcr1 bits in pwcr to select a conversion period of either. on the h8/38104 group, the output format is selected using the pwcr2 bit. refer to section 9.4, asynchronous event counter, for information on how to select event counter pwm (pwm incorporating aec), one of the two available output formats.
rev. 4.00, 03/04, page xxvii of l item page revisions (see manual for details) 12.1 features 293 description amended conversion time: at least 12.4 s per channel (at 5 mhz operation)/ 7.8 s (at 8 mhz operation) * note: * h8/38104 group only. 13.1 features 305 description added removal of split-resistance can be controlled in software. note that this capability is implemented in the h8/38104 group only. figure 13.1 (1) block diagram of lcd controller/driver (h8/3802 group, h8/38004 group) figure 13.1(2) block diagram of lcd controller/driver (h8/38104 group) 306, 307 figure 13.1(1) : title amended figure 13.1(2) : newly added 13.3.3 lcd control register 2 (lcr2) 313 description amended lcr2 controls switching between the a waveform and b waveform and removal of split-resistance. note that removal of split-resistance control is only implemented on the h8/38104 group. bit table amended 3to0 * cds3 cds2 cds1 cds0 all 0 r/w removal of split-resistance control these bits control whether the split- resistance is removed or connected. cds3 = 0, cds2 = cds1 = cds0 = 1: split-resistance removed all other settings: split-resistance connected note: * applies to h8/38104 group only. on the h8/3802 group or h8/38004 group, these bits are reserved like bit 4. section 14 power-on reset and low-voltage detection circuits (h8/38104 group only) 323 to 334 newly added section 15 power supply circuit (h8/38104 group only) 335, 336 newly added
rev. 4.00, 03/04, page xxviii of l item page revisions (see manual for details) 338 table and notes added 16.1 register addresses (address order) low-voltage detection control register * 4 lvdcr 8 h'ff86 lvd 8 2 low-voltage detection status register * 4 lvdsr 8 h'ff87 lvd 8 2 339 low-voltage detection counter * 4 lvdcnt 8 h'ffc3 lvd 8 2 340 oscillator control register * 4 osccr 8 h'fff5 cpg 8 2 interrupt request register 1 irr1 8 h'fff6 interru pts 82 interrupt request register 2 irr2 8 h'fff7 interru pts 82 timer mode register w * 4 tmw 8 h'fff8 wdt * 2 8 2 note: 4. h8/38104 group only 16.2 register bits 341 table and notes added lvdcr * 4 lvde ? vintdsel vintusel lvdsl lvdre lvdde lvdue lvdsr * 4 ovf ? ? ? vrefsel ? lvddf lvduf low-voltage detect circuit 342 lcr ? psw act disp cks3 cks2 cks1 cks0 lcr2 lcdab ? ? ? cds3 * 4 cds2 * 4 cds1 * 4 cds0 * 4 lvdcnt * 4 cnt7 cnt6 cnt5 cnt4 cnt3 cnt2 cnt1 cnt0 low-voltage detect circuit pwcr2 ? ? ? ? ? pwcr22 * 4 pwcr21 pwcr20 10-bit pwm pwdru2 ? ? ? ? ? ? pwdru21 pwdru20 pwdrl2 pwdrl27 pwdrl26 pwdrl25 pwdrl24 pwdrl23 pwdrl22 pwdrl21 pwdrl20 pwcr1 ? ? ? ? ? pwcr12 * 4 pwcr11 pwcr10 pwdru1 ? ? ? ? ? ? pwdru11 pwdru10 pwdrl1 pwdrl17 pwdrl16 pwdrl15 pwdrl14 pwdrl13 pwdrl12 pwdrl11 pwdrl10 343 osccr * 4 substp ? ? ? ? irqaecf oscf ? cpg tmw * 4 ? ? ? ? cks3 cks2 cks1 cks0 wdt * 2 iw pr iw pf7 iw pf6 iw pf5 iw pf4 iw pf3 iw pf2 iw pf1 iw pf0 ckstpr1 ? ? s32ckstp adckstp ? tfckstp ? tackstp system ckstpr2 lvdckstp * 4 ? ? pw2ckstp aeckstp wdckstp pw1ckstp ldckstp note: 4. h8/38104 group only
rev. 4.00, 03/04, page xxix of l item page revisions (see manual for details) 344 table and notes added 16.3 register states in each operation mode lvdcr * 4 initialized ? ? ? ? ? ? lvdsr * 4 initialized ? ? ? ? ? ? low-voltage detect circuit 345 lvdcnt * 4 initialized ? ? ? ? ? ? low-voltage detect circuit 346 osccr * 4 initialized ? ? ? ? ? ? cpg tmw * 4 initialized ? ? ? ? ? ? wdt * 2 note: 4. h8/38104 group only 369 table amended v cc =2.2vto 3.6 v i ol =10.0ma 17.4.2 dc characteristics table 17.8 dc characteristics output low voltage v ol p90 to p95 v cc =1.8vto 3.6 v i ol =8.0ma ?? 0.5 v 370 active mode current consump- tion i ope1 v cc active (high- speed) mode v cc =1.8v, f osc = 2mhz ? 0.4 ? ma * 1 * 3 * 4 approx. max. value = 1.1 typ. i ope2 v cc active (medium- speed) mode v cc =1.8v, f osc = 2mhz, osc /128 ? 0.06 ? ma * 1 * 3 * 4 approx. max. value = 1.1 typ. 371 sleep mode current consump- tion i sleep v cc v cc =1.8v, f osc = 2mhz ? 0.16 ? ma * 1 * 3 * 4 approx. max. value = 1.1 typ. 373 ?i oh v cc =2.2vto 3.6 v ? ? 2.0 ma allowable output high current (per pin) all output pins other than above ? ? 0.2
rev. 4.00, 03/04, page xxx of l item page revisions (see manual for details) 17.5 absolute maximum ratings of h8/38104 group 384 newly added 17.6 electrical characteristics of h8/38104 group 385 to 408 newly added a.1 instruction list table a.1 instruction set 423 notes amended (4) the number of states required for execution is 4n + 9 (n = value of r4l). in the h8/38004 group and h8/38104 group, the number of states required for execution is 4n + 8. a.3 number of execution states table a.3 number of states required for execution 427 note amended note: * depends on which on-chip peripheral module is accessed. see section 16.1, register addresses (address order). appendix d product code lineup table d.3 product code lineup of h8/38104 group 449 newly added appendix e package dimensions 451 description amended the package dimensions for the h8/38027 group, h8/38004 group, and h8/38104 group are shown in figure e.1 (fp-64a), figure e.2 (fp- 64e), and figure e.3 (dp-64s).
rev. 4.00, 03/04, page xxxi of l contents section 1 overview ............................................................................................................. 1 1.1 features .................................................................................................................... ......... 1 1.2 internal block diagram..................................................................................................... 4 1.3 pin arrangement .............................................................................................................. .7 1.4 pin functions ................................................................................................................ .... 19 section 2 cpu ...................................................................................................................... 23 2.1 features .................................................................................................................... ......... 23 2.2 address space and memory map ..................................................................................... 24 2.3 register configuration...................................................................................................... 3 2 2.3.1 general registers ................................................................................................. 33 2.3.2 program counter (pc) ......................................................................................... 33 2.3.3 condition code register (ccr) .......................................................................... 34 2.3.4 initial register values.......................................................................................... 35 2.4 data formats ................................................................................................................. .... 35 2.4.1 general register data formats ............................................................................ 35 2.4.2 memory data formats ......................................................................................... 37 2.5 instruction set .............................................................................................................. ..... 38 2.5.1 data transfer instructions.................................................................................... 40 2.5.2 arithmetic operations instructions ...................................................................... 42 2.5.3 logic operations instructions .............................................................................. 43 2.5.4 shift instructions.................................................................................................. 43 2.5.5 bit manipulation instructions .............................................................................. 45 2.5.6 branch instructions .............................................................................................. 48 2.5.7 system control instructions................................................................................. 50 2.5.8 block data transfer instructions ......................................................................... 51 2.6 addressing modes and effective address ........................................................................ 52 2.6.1 addressing modes ............................................................................................... 52 2.6.2 effective address calculation.............................................................................. 54 2.7 basic bus cycle ............................................................................................................... .58 2.7.1 access to on-chip memory (ram, rom)......................................................... 58 2.7.2 on-chip peripheral modules ............................................................................... 59 2.8 cpu states ................................................................................................................... ..... 61 2.9 usage notes .................................................................................................................. .... 62 2.9.1 notes on data access to empty areas ................................................................ 62 2.9.2 access to internal i/o registers........................................................................... 62 2.9.3 eepmov instruction........................................................................................... 63 2.9.4 bit manipulation instructions .............................................................................. 63
rev. 4.00, 03/04, page xxxii of l section 3 exception handling ......................................................................................... 69 3.1 exception sources and vector address ............................................................................ 70 3.2 register descriptions ........................................................................................................ 72 3.2.1 interrupt edge select register (iegr) ................................................................ 72 3.2.2 interrupt enable register 1 (ienr1) ................................................................... 73 3.2.3 interrupt enable register 2 (ienr2) ................................................................... 74 3.2.4 interrupt request register 1 (irr1) .................................................................... 75 3.2.5 interrupt request register 2 (irr2) .................................................................... 76 3.2.6 wakeup interrupt request register (iwpr)........................................................ 77 3.2.7 wakeup edge select register (wegr)............................................................... 77 3.3 reset exception handling................................................................................................. 78 3.4 interrupt exception handling............................................................................................ 78 3.4.1 external interrupts ............................................................................................... 78 3.4.2 internal interrupts ................................................................................................ 79 3.4.3 interrupt handling sequence ............................................................................... 80 3.4.4 interrupt response time...................................................................................... 81 3.5 usage notes .................................................................................................................. .... 83 3.5.1 interrupts after reset............................................................................................ 83 3.5.2 notes on stack area use ..................................................................................... 83 3.5.3 notes on rewriting port mode registers............................................................. 83 3.5.4 interrupt request flag clearing method.............................................................. 85 section 4 clock pulse generators ................................................................................... 87 4.1 features.................................................................................................................... ......... 87 4.2 register description......................................................................................................... .89 4.3 system clock generator ................................................................................................... 90 4.3.1 connecting crystal resonator ............................................................................. 90 4.3.2 connecting ceramic resonator ........................................................................... 91 4.3.3 external clock input method............................................................................... 92 4.3.4 on-chip oscillator selection method (h8/38104 group only) .......................... 92 4.4 subclock generator........................................................................................................... 93 4.4.1 connecting 32.768-khz/38.4-khz crystal resonator.......................................... 93 4.4.2 pin connection when not using subclock.......................................................... 94 4.4.3 external clock input ............................................................................................ 94 4.5 prescalers .................................................................................................................. ........ 95 4.5.1 prescaler s ........................................................................................................... 95 4.5.2 prescaler w.......................................................................................................... 95 4.6 usage notes .................................................................................................................. .... 95 4.6.1 note on resonators.............................................................................................. 95 4.6.2 notes on board design ........................................................................................ 97 4.6.3 definition of oscillation stabilization standby time.......................................... 98 4.6.4 notes on use of crystal resonator (excluding ceramic resonator)................... 99 4.6.5 notes on h8/38104 group ................................................................................... 100
rev. 4.00, 03/04, page xxxiii of l section5 power-downmodes ........................................................................................ 101 5.1 register descriptions ........................................................................................................ 102 5.1.1 system control register 1 (syscr1) ................................................................. 102 5.1.2 system control register 2 (syscr2) ................................................................. 104 5.1.3 clock halt registers 1 and 2 (ckstpr1 and ckstpr2) .................................. 105 5.2 mode transitions and states of lsi.................................................................................. 106 5.2.1 sleep mode .......................................................................................................... 110 5.2.2 standby mode ...................................................................................................... 111 5.2.3 watch mode......................................................................................................... 111 5.2.4 subsleep mode..................................................................................................... 112 5.2.5 subactive mode ................................................................................................... 112 5.2.6 active (medium-speed) mode ............................................................................ 113 5.3 direct transition ............................................................................................................ ... 113 5.3.1 direct transition from active (high-speed) mode to active (medium-speed) mode .................................................................................................................... 114 5.3.2 direct transition from active (medium-speed) mode to active (high-speed) mode .................................................................................................................... 115 5.3.3 direct transition from subactive mode to active (high-speed) mode .............. 115 5.3.4 direct transition from subactive mode to active (medium-speed) mode ........ 116 5.3.5 notes on external input signal changes before/after direct transition.............. 116 5.4 module standby function ................................................................................................. 117 5.5 usage notes .................................................................................................................. .... 117 5.5.1 standby mode transition and pin states ............................................................. 117 5.5.2 notes on external input signal changes before/after standby mode.................. 117 section 6 rom ..................................................................................................................... 119 6.1 block diagram ................................................................................................................ .. 119 6.2 h8/3802 prom mode ...................................................................................................... 120 6.2.1 setting to prom mode ....................................................................................... 120 6.2.2 socket adapter pin arrangement and memory map........................................... 120 6.3 h8/3802 programming...................................................................................................... 123 6.3.1 writing and verifying.......................................................................................... 123 6.3.2 programming precautions .................................................................................... 127 6.4 reliability of programmed data ....................................................................................... 128 6.5 overview of flash memory .............................................................................................. 129 6.5.1 features................................................................................................................ 12 9 6.5.2 block diagram..................................................................................................... 130 6.5.3 block configuration............................................................................................. 131 6.6 register descriptions ........................................................................................................ 132 6.6.1 flash memory control register 1 (flmcr1)..................................................... 133 6.6.2 flash memory control register 2 (flmcr2)..................................................... 134 6.6.3 erase block register (ebr) ................................................................................ 134 6.6.4 flash memory power control register (flpwcr) ............................................ 135
rev. 4.00, 03/04, page xxxiv of l 6.6.5 flash memory enable register (fenr) .............................................................. 135 6.7 on-board programming modes........................................................................................ 136 6.7.1 boot mode ........................................................................................................... 136 6.7.2 programming/erasing in user program mode..................................................... 139 6.7.3 notes on on-board programming ....................................................................... 140 6.8 flash memory programming/erasing ............................................................................... 141 6.8.1 program/program-verify ..................................................................................... 141 6.8.2 erase/erase-verify............................................................................................... 144 6.8.3 interrupt handling when programming/erasing flash memory.......................... 144 6.9 program/erase protection ................................................................................................. 146 6.9.1 hardware protection ............................................................................................ 146 6.9.2 software protection.............................................................................................. 146 6.9.3 error protection.................................................................................................... 146 6.10 programmer mode ............................................................................................................ 1 47 6.10.1 socket adapter..................................................................................................... 147 6.10.2 programmer mode commands ............................................................................ 147 6.10.3 memory read mode ............................................................................................ 150 6.10.4 auto-program mode ............................................................................................ 152 6.10.5 auto-erase mode................................................................................................. 154 6.10.6 status read mode ................................................................................................ 156 6.10.7 status polling ....................................................................................................... 157 6.10.8 programmer mode transition time .................................................................... 158 6.10.9 notes on memory programming.......................................................................... 158 6.11 power-down states for flash memory............................................................................. 159 section 7 ram ..................................................................................................................... 161 7.1 block diagram................................................................................................................ .. 162 section 8 i/o ports .............................................................................................................. 163 8.1 port 3....................................................................................................................... .......... 165 8.1.1 port data register 3 (pdr3)................................................................................ 166 8.1.2 port control register 3 (pcr3) ........................................................................... 166 8.1.3 port pull-up control register 3 (pucr3)........................................................... 167 8.1.4 port mode register 3 (pmr3) ............................................................................. 168 8.1.5 port mode register 2 (pmr2) ............................................................................. 169 8.1.6 pin functions ....................................................................................................... 170 8.1.7 input pull-up mos.............................................................................................. 171 8.2 port 4....................................................................................................................... .......... 172 8.2.1 port data register 4 (pdr4)................................................................................ 172 8.2.2 port control register 4 (pcr4) ........................................................................... 173 8.2.3 serial port control register (spcr).................................................................... 173 8.2.4 pin functions ....................................................................................................... 175 8.3 port 5....................................................................................................................... .......... 176
rev. 4.00, 03/04, page xxxv of l 8.3.1 port data register 5 (pdr5)................................................................................ 177 8.3.2 port control register 5 (pcr5) ........................................................................... 177 8.3.3 port pull-up control register 5 (pucr5)........................................................... 178 8.3.4 port mode register 5 (pmr5) ............................................................................. 178 8.3.5 pin functions ....................................................................................................... 179 8.3.6 input pull-up mos.............................................................................................. 180 8.4 port 6....................................................................................................................... .......... 180 8.4.1 port data register 6 (pdr6)................................................................................ 181 8.4.2 port control register 6 (pcr6) ........................................................................... 181 8.4.3 port pull-up control register 6 (pucr6)........................................................... 182 8.4.4 pin functions ....................................................................................................... 182 8.4.5 input pull-up mos.............................................................................................. 183 8.5 port 7....................................................................................................................... .......... 184 8.5.1 port data register 7 (pdr7)................................................................................ 184 8.5.2 port control register 7 (pcr7) ........................................................................... 185 8.5.3 pin functions ....................................................................................................... 185 8.6 port 8....................................................................................................................... .......... 186 8.6.1 port data register 8 (pdr8)................................................................................ 187 8.6.2 port control register 8 (pcr8) ........................................................................... 187 8.6.3 pin functions ....................................................................................................... 187 8.7 port 9....................................................................................................................... .......... 188 8.7.1 port data register 9 (pdr9)................................................................................ 188 8.7.2 port mode register 9 (pmr9) ............................................................................. 189 8.7.3 pin functions ....................................................................................................... 189 8.8 port a....................................................................................................................... ......... 190 8.8.1 port data register a (pdra).............................................................................. 190 8.8.2 port control register a (pcra).......................................................................... 191 8.8.3 pin functions ....................................................................................................... 191 8.9 port b ....................................................................................................................... ......... 192 8.9.1 port data register b (pdrb) .............................................................................. 193 8.9.2 port mode register b (pmrb)............................................................................ 193 8.9.3 pin functions ....................................................................................................... 194 8.10 usage notes ................................................................................................................. ..... 195 8.10.1 how to handle unused pin.................................................................................. 195 section 9 timers .................................................................................................................. 197 9.1 overview.................................................................................................................... ....... 197 9.2 timer a...................................................................................................................... ....... 199 9.2.1 features................................................................................................................ 19 9 9.2.2 register descriptions ........................................................................................... 200 9.2.3 operation ............................................................................................................. 202 9.2.4 timer a operating states .................................................................................... 202 9.3 timer f...................................................................................................................... ........ 203
rev. 4.00, 03/04, page xxxvi of l 9.3.1 features................................................................................................................ 20 3 9.3.2 input/output pins................................................................................................. 204 9.3.3 register descriptions ........................................................................................... 205 9.3.4 cpu interface ...................................................................................................... 209 9.3.5 operation ............................................................................................................. 211 9.3.6 timer f operating states ..................................................................................... 214 9.3.7 usage notes ......................................................................................................... 214 9.4 asynchronous event counter (aec)................................................................................ 218 9.4.1 features................................................................................................................ 21 8 9.4.2 input/output pins................................................................................................. 220 9.4.3 register descriptions ........................................................................................... 220 9.4.4 operation ............................................................................................................. 227 9.4.5 operating states of asynchronous event counter............................................... 232 9.4.6 usage notes ......................................................................................................... 232 9.5 watchdog timer ............................................................................................................... 234 9.5.1 features................................................................................................................ 23 4 9.5.2 register descriptions ........................................................................................... 235 9.5.3 operation ............................................................................................................. 238 9.5.4 operating states of watchdog timer................................................................... 239 section 10 serial communication interface 3 (sci3) .............................................. 241 10.1 features................................................................................................................... .......... 241 10.2 input/output pins ........................................................................................................... ... 243 10.3 register descriptions ....................................................................................................... . 243 10.3.1 receive shift register (rsr) .............................................................................. 243 10.3.2 receive data register (rdr) .............................................................................. 243 10.3.3 transmit shift register (tsr) ............................................................................. 244 10.3.4 transmit data register (tdr)............................................................................. 244 10.3.5 serial mode register (smr) ............................................................................... 244 10.3.6 serial control register 3 (scr3)......................................................................... 246 10.3.7 serial status register (ssr) ................................................................................ 248 10.3.8 bit rate register (brr) ...................................................................................... 250 10.3.9 serial port control register (spcr).................................................................... 255 10.4 operation in asynchronous mode .................................................................................... 256 10.4.1 clock.................................................................................................................... 257 10.4.2 sci3 initialization................................................................................................ 261 10.4.3 data transmission ............................................................................................... 262 10.4.4 serial data reception .......................................................................................... 264 10.5 operation in clocked synchronous mode ........................................................................ 268 10.5.1 clock.................................................................................................................... 268 10.5.2 sci3 initialization................................................................................................ 268 10.5.3 serial data transmission ..................................................................................... 269 10.5.4 serial data reception (clocked synchronous mode).......................................... 271
rev. 4.00, 03/04, page xxxvii of l 10.5.5 simultaneous serial data transmission and reception....................................... 273 10.6 multiprocessor communication function......................................................................... 274 10.6.1 multiprocessor serial data transmission ............................................................ 276 10.6.2 multiprocessor serial data reception ................................................................. 277 10.7 interrupts ................................................................................................................. .......... 280 10.8 usage notes ................................................................................................................. ..... 282 10.8.1 break detection and processing........................................................................... 282 10.8.2 mark state and break sending............................................................................. 282 10.8.3 receive error flags and transmit operations (clocked synchronous mode only) .................................................................................................................... 283 10.8.4 receive data sampling timing and reception margin in asynchronous mode 283 10.8.5 note on switching sck32 function.................................................................... 284 10.8.6 relation between writing to tdr and bit tdre ............................................... 285 10.8.7 relation between rdr reading and bit rdrf ................................................... 285 10.8.8 transmit and receive operations when making state transition....................... 286 10.8.9 setting in subactive or subsleep mode ............................................................... 286 10.8.10 oscillator use with serial communications interface 3 (h8/38104 group only) 286 section 11 10-bit pwm ..................................................................................................... 287 11.1 features ................................................................................................................... .......... 287 11.2 input/output pins ........................................................................................................... ... 288 11.3 register descriptions ....................................................................................................... . 289 11.3.1 pwm control register (pwcr).......................................................................... 289 11.3.2 pwm data registers u and l (pwdru, pwdrl)............................................ 290 11.4 operation.................................................................................................................. ......... 291 11.4.1 operation ............................................................................................................. 291 11.4.2 pwm operating states......................................................................................... 292 section 12 a/d converter ................................................................................................. 293 12.1 features ................................................................................................................... .......... 293 12.2 input/output pins ........................................................................................................... ... 295 12.3 register descriptions ....................................................................................................... . 295 12.3.1 a/d result registers h and l (adrrh and adrrl)....................................... 295 12.3.2 a/d mode register (amr) ................................................................................. 296 12.3.3 a/d start register (adsr).................................................................................. 296 12.4 operation.................................................................................................................. ......... 297 12.4.1 a/d conversion ................................................................................................... 297 12.4.2 operating states of a/d converter ...................................................................... 297 12.5 example of use............................................................................................................... .. 298 12.6 a/d conversion accuracy definitions ............................................................................. 301 12.7 usage notes ................................................................................................................. ..... 302 12.7.1 permissible signal source impedance ................................................................. 302 12.7.2 influences on absolute accuracy ........................................................................ 302
rev. 4.00, 03/04, page xxxviii of l 12.7.3 usage notes ......................................................................................................... 303 section 13 lcd controller/driver ................................................................................. 305 13.1 features................................................................................................................... .......... 305 13.2 input/output pins ........................................................................................................... ... 308 13.3 register descriptions ....................................................................................................... . 309 13.3.1 lcd port control register (lpcr)..................................................................... 309 13.3.2 lcd control register (lcr)............................................................................... 311 13.3.3 lcd control register 2 (lcr2).......................................................................... 313 13.4 operation .................................................................................................................. ........ 314 13.4.1 settings up to lcd display ................................................................................. 314 13.4.2 relationship between lcd ram and display.................................................... 315 13.4.3 operation in power-down modes ....................................................................... 320 13.4.4 boosting lcd drive power supply..................................................................... 321 section 14 power-on reset and low-voltage detection circuits (h8/38104 group only) ............................................................................... 323 14.1 features................................................................................................................... .......... 323 14.2 register descriptions ....................................................................................................... . 325 14.2.1 low-voltage detection control register (lvdcr) ........................................... 325 14.2.2 low-voltage detection status register (lvdsr) .............................................. 326 14.2.3 low-voltage detection counter (lvdcnt) ...................................................... 327 14.3 operation .................................................................................................................. ........ 328 14.3.1 power-on reset circuit ....................................................................................... 328 14.3.2 low-voltage detection circuit............................................................................ 329 section 15 power supply circuit (h8/38104 group only) .................................... 335 15.1 when using internal power supply step-down circuit................................................... 335 15.2 when not using internal power supply step-down circuit............................................ 336 section 16 list of registers .............................................................................................. 337 16.1 register addresses (address order)................................................................................. 338 16.2 register bits............................................................................................................... ....... 341 16.3 register states in each operating mode .......................................................................... 344 section 17 electrical characteristics ............................................................................. 347 17.1 absolute maximum ratings of h8/3802 group ............................................................... 347 17.2 electrical characteristics of h8/3802 group .................................................................... 348 17.2.1 power supply voltage and operating ranges ..................................................... 348 17.2.2 dc characteristics ............................................................................................... 351 17.2.3 ac characteristics ............................................................................................... 358 17.2.4 a/d converter characteristics ............................................................................. 360 17.2.5 lcd characteristics............................................................................................. 362
rev. 4.00, 03/04, page xxxix of l 17.3 absolute maximum ratings of h8/38004 group ............................................................. 363 17.4 electrical characteristics of h8/38004 group .................................................................. 364 17.4.1 power supply voltage and operating ranges ..................................................... 364 17.4.2 dc characteristics ............................................................................................... 368 17.4.3 ac characteristics ............................................................................................... 375 17.4.4 a/d converter characteristics ............................................................................. 379 17.4.5 lcd characteristics............................................................................................. 381 17.4.6 flash memory characteristics.............................................................................. 382 17.5 absolute maximum ratings of h8/38104 group ............................................................. 384 17.6 electrical characteristics of h8/38104 group .................................................................. 385 17.6.1 power supply voltage and operating ranges ..................................................... 385 17.6.2 dc characteristics ............................................................................................... 389 17.6.3 ac characteristics ............................................................................................... 398 17.6.4 a/d converter characteristics ............................................................................. 400 17.6.5 lcd characteristics............................................................................................. 401 17.6.6 flash memory characteristics.............................................................................. 402 17.6.7 power supply voltage detection circuit characteristics (preliminary) .............. 404 17.6.8 power-on reset circuit characteristics (preliminary) ........................................ 407 17.6.9 watchdog timer characteristics.......................................................................... 408 17.7 operation timing............................................................................................................ .. 408 17.8 output load condition ..................................................................................................... 409 17.9 resonator equivalent circuit ............................................................................................ 410 17.10 usage note................................................................................................................. ....... 411 appendix a instruction set .............................................................................................. 413 a.1 instruction list ............................................................................................................. ..... 413 a.2 operation code map......................................................................................................... 424 a.3 number of execution states.............................................................................................. 426 appendix b i/o port block diagrams ........................................................................... 433 b.1 port 3 block diagrams ...................................................................................................... 433 b.2 port 4 block diagrams ...................................................................................................... 435 b.3 port 5 block diagram ....................................................................................................... 439 b.4 port 6 block diagram ....................................................................................................... 440 b.5 port 7 block diagram ....................................................................................................... 441 b.6 port 8 block diagram ....................................................................................................... 442 b.7 port 9 block diagrams ...................................................................................................... 442 b.8 port a block diagram....................................................................................................... 443 b.9 port b block diagram....................................................................................................... 444 appendix c port states in each operating state ....................................................... 445 appendix d product code lineup ................................................................................. 446
rev. 4.00, 03/04, page xl of l appendix e package dimensions ................................................................................... 451 appendix f chip form specifications .......................................................................... 454 appendix g bonding pad form ...................................................................................... 456 appendix h chip tray specifications .......................................................................... 457 index ............................................................................................................................... ........... 461
rev. 4.00, 03/04, page xli of l figures section 1 overview figure 1.1 internal block diagram of h8/3802 group ....................................................... 4 figure 1.2 internal block diagram of h8/38004 group ..................................................... 5 figure 1.3 internal block diagram of h8/38104 group ..................................................... 6 figure 1.4 pin arrangement of h8/3802 and h8/38004 group (fp-64a, fp-64e)............ 7 figure 1.5 pin arrangement of h8/3802 group (dp-64s).................................................. 8 figure 1.6 pin arrangement of h8/38104 group (fp-64a, fp-64e) ................................. 9 figure 1.7 pad arrangement of hcd6433802, hcd6433801, and hcd6433800 (top view)......................................................................................................... 10 figure 1.8 pad arrangement of hcd64338004, hcd64338003, hcd64338002, hcd64338001, and hcd64338000 (top view) .............................................. 13 figure 1.9 pad arrangement of hcd64f38004 and hcd64f38002 (top view).............. 16 section 2 cpu figure 2.1(1) h8/3802 memory map ...................................................................................... 24 figure 2.1(2) h8/3801 memory map ...................................................................................... 25 figure 2.1(3) h8/3800 memory map ...................................................................................... 26 figure 2.1(4) h8/38004, h8/38104 memory map................................................................... 27 figure 2.1(5) h8/38003, h8/38103 memory map................................................................... 28 figure 2.1(6) h8/38002, h8/38102 memory map................................................................... 29 figure 2.1(7) h8/38001, h8/38101 memory map................................................................... 30 figure 2.1(8) h8/38000, h8/38100 memory map................................................................... 31 figure 2.2 cpu registers.................................................................................................... 32 figure 2.3 stack pointer ...................................................................................................... 33 figure 2.4 general register data formats .......................................................................... 36 figure 2.5 memory data formats ....................................................................................... 37 figure 2.6 instruction formats of data transfer instructions ............................................. 41 figure 2.7 instruction formats of arithmetic, logic, and shift instructions ...................... 44 figure 2.8 instruction formats of bit manipulation instructions........................................ 47 figure 2.9 instruction formats of branch instructions........................................................ 49 figure 2.10 instruction formats of system control instructions .......................................... 50 figure 2.11 instruction format of block data transfer instructions .................................... 51 figure 2.12 on-chip memory access cycle ........................................................................ 58 figure 2.13 on-chip peripheral module access cycle (2-state access) ............................. 59 figure 2.14 on-chip peripheral module access cycle (3-state access) ............................. 60 figure 2.15 cpu operation states ........................................................................................ 61 figure 2.16 state transitions................................................................................................. 62 figure 2.17 example of timer configuration with two registers allocated to same address .............................................................................................................. 63
rev. 4.00, 03/04, page xlii of l section 3 exception handling figure 3.1 reset sequence .................................................................................................. 79 figure 3.2 stack status after exception handling............................................................... 81 figure 3.3 interrupt sequence ............................................................................................. 82 figure 3.4 port mode register setting and interrupt request flag clearing procedure..... 85 section 4 clock pulse generators figure 4.1 block diagram of clock pulse generators (h8/3802, h8/38004 group).......... 87 figure 4.2 block diagram of clock pulse generators (h8/38104 group) ......................... 88 figure 4.3 block diagram of system clock generator....................................................... 90 figure 4.4(1) typical connection to crystal resonator (h8/3802 group) ............................. 90 figure 4.4(2) typical connection to crystal resonator (h8/38004, h8/38104 group).......... 91 figure 4.5 equivalent circuit of crystal resonator ............................................................ 91 figure 4.6(1) typical connection to ceramic resonator (h8/3802 group) ........................... 91 figure 4.6(2) typical connection to ceramic resonator (h8/38004, h8/38104 group)........ 92 figure 4.7 example of external clock input....................................................................... 92 figure 4.8 block diagram of subclock generator .............................................................. 93 figure 4.9 typical connection to 32.768-khz/38.4-khz crystal resonator ...................... 93 figure 4.10 equivalent circuit of 32.768-khz/38.4-khz crystal resonator ........................ 94 figure 4.11 pin connection when not using subclock........................................................ 94 figure 4.12 pin connection when inputting external clock................................................. 94 figure 4.13 example of crystal and ceramic resonator arrangement ................................ 96 figure 4.14 negative resistor measurement and proposed changes in circuit ................... 97 figure 4.15 example of incorrect board design................................................................... 97 figure 4.16 oscillation stabilization standby time ............................................................. 98 section 5 power-down modes figure 5.1 mode transition diagram.................................................................................. 107 figure 5.2 standby mode transition and pin states ........................................................... 117 figure 5.3 external input signal capture when signal changes before/after standby mode or watch mode .................................................................................................. 118 section 6 rom figure 6.1 block diagram of rom (h8/3802) ................................................................... 119 figure 6.2 socket adapter pin correspondence (with hn27c101).................................... 121 figure 6.3 h8/3802 memory map in prom mode............................................................ 122 figure 6.4 high-speed, high-reliability programming flowchart .................................... 124 figure 6.5 prom write/verify timing.............................................................................. 127 figure 6.6 recommended screening procedure ................................................................. 128 figure 6.7 block diagram of flash memory ...................................................................... 130 figure 6.8(1) block configuration of 32-kbyte flash memory............................................... 131 figure 6.8(2) block configuration of 16-kbyte flash memory............................................... 132 figure 6.9 programming/erasing flowchart example in user program mode .................. 140
rev. 4.00, 03/04, page xliii of l figure 6.10 program/program-verify flowchart .................................................................. 142 figure 6.11 erase/erase-verify flowchart............................................................................ 145 figure 6.12(1) socket adapter pin correspondence diagram (h8/38004f, h8/38002f) ......... 148 figure 6.12(2) socket adapter pin correspondence diagram (h8/38104f, h8/38102f) ......... 149 figure 6.13 timing waveforms for memory read after command write........................... 150 figure 6.14 timing waveforms in transition from memory read mode to another mode 151 figure 6.15 timing waveforms in ce and oe enable state read....................................... 152 figure 6.16 timing waveforms in ce and oe clock system read..................................... 152 figure 6.17 timing waveforms in auto-program mode...................................................... 154 figure 6.18 timing waveforms in auto-erase mode........................................................... 155 figure 6.19 timing waveforms in status read mode.......................................................... 156 figure 6.20 oscillation stabilization time, boot program transfer time, and power-down sequence ............................................................................................................ 158 section 7 ram figure 7.1 block diagram of ram (h8/3802) ................................................................... 162 section 8 i/o ports figure 8.1 port 3 pin configuration .................................................................................... 165 figure 8.2 port 4 pin configuration .................................................................................... 172 figure 8.3 input/output data inversion function ............................................................... 173 figure 8.4 port 5 pin configuration .................................................................................... 176 figure 8.5 port 6 pin configuration .................................................................................... 180 figure 8.6 port 7 pin configuration .................................................................................... 184 figure 8.7 port 8 pin configuration .................................................................................... 186 figure 8.8 port 9 pin configuration .................................................................................... 188 figure 8.9 port a pin configuration ................................................................................... 190 figure 8.10 port b pin configuration.................................................................................... 192 section 9 timers figure 9.1 block diagram of timer a ................................................................................ 200 figure 9.2 block diagram of timer f................................................................................. 204 figure 9.3 write access to tcf (cpu tcf) ................................................................. 210 figure 9.4 read access to tcf (tcf cpu) .................................................................. 211 figure 9.5 tmofh/tmofl output timing ...................................................................... 213 figure 9.6 clear interrupt request flag when interrupt source generation signal is valid 217 figure 9.7 block diagram of asynchronous event counter............................................... 219 figure 9.8 example of software processing when using ech and ecl as 16-bit event counter............................................................................................................... 228 figure 9.9 example of software processing when using ech and ecl as 8-bit event counters ............................................................................................................. 229 figure 9.10 event counter operation waveform ................................................................. 230 figure 9.11 example of clock control operation ................................................................ 231
rev. 4.00, 03/04, page xliv of l figure 9.12(1) block diagram of watchdog timer (h8/38004 group).................................... 234 figure 9.12(2) block diagram of watchdog timer (h8/38104 group).................................... 235 figure 9.13 example of watchdog timer operation ............................................................ 238 section 10 serial communication interface 3 (sci3) figure 10.1 block diagram of sci3 ..................................................................................... 242 figure 10.2 data format in asynchronous communication................................................. 256 figure 10.3 relationship between output clock and transfer data phase (asynchronous mode) (example with 8-bit data, parity, two stop bits)........ 257 figure 10.4 sample sci3 initialization flowchart................................................................ 261 figure 10.5 example sci3 operation in transmission in asynchronous mode (8-bit data, parity, one stop bit)...................................................................... 262 figure 10.6 sample serial transmission flowchart (asynchronous mode)......................... 263 figure 10.7 example sci3 operation in reception in asynchronous mode (8-bit data, parity, one stop bit)...................................................................... 265 figure 10.8 sample serial data reception flowchart (asynchronous mode) (1)................ 266 figure 10.8 sample serial data reception flowchart (asynchronous mode) (2)................ 267 figure 10.9 data format in clocked synchronous communication..................................... 268 figure 10.10 example of sci3 operation in transmission in clocked synchronous mode .. 269 figure 10.11 sample serial transmission flowchart (clocked synchronous mode)............. 270 figure 10.12 example of sci3 reception operation in clocked synchronous mode ........... 271 figure 10.13 sample serial reception flowchart (clocked synchronous mode) .................. 272 figure 10.14 sample flowchart of simultaneous serial transmit and receive operations (clocked synchronous mode) ........................................................................... 273 figure 10.15 example of communication using multiprocessor format (transmission of data h?aa to receiving station a) ...................................... 275 figure 10.16 sample multiprocessor serial transmission flowchart..................................... 276 figure 10.17 sample multiprocessor serial reception flowchart (1) .................................... 277 figure 10.17 sample multiprocessor serial reception flowchart (2) .................................... 278 figure 10.18 example of sci3 operation in reception using multiprocessor format (example with 8-bit data, multiprocessor bit, one stop bit) .......................... 279 figure 10.19(a) rdrf setting and rxi interrupt ....................................................................... 281 figure 10.19(b) tdre setting and txi interrupt ....................................................................... 282 figure 10.19(c) tend setting and tei interrupt........................................................................ 282 figure 10.20 receive data sampling timing in asynchronous mode................................... 284 figure 10.21 relation between rdr read timing and data ................................................. 285 section 11 10-bit pwm figure 11.1(1) block diagram of 10-bit pwm (h8/3802 group, h8/38004 group) ............... 287 figure 11.1(2) block diagram of 10-bit pwm (h8/38104 group) .......................................... 288 figure 11.2 waveform output by 10-bit pwm.................................................................... 291
rev. 4.00, 03/04, page xlv of l section 12 a/d converter figure 12.1 block diagram of a/d converter ...................................................................... 294 figure 12.2 example of a/d conversion operation............................................................. 299 figure 12.3 flowchart of procedure for using a/d converter (polling by software).......... 300 figure 12.4 flowchart of procedure for using a/d converter (interrupts used)................. 300 figure 12.5 a/d conversion accuracy definitions (1) ........................................................ 301 figure 12.6 a/d conversion accuracy definitions (2) ........................................................ 302 figure 12.7 example of analog input circuit....................................................................... 303 section 13 lcd controller/driver figure 13.1(1) block diagram of lcd controller/driver (h8/3802 group, h8/38004 group) 306 figure 13.1(2) block diagram of lcd controller/driver (h8/38104 group) .......................... 307 figure 13.2 handling of lcd drive power supply when using 1/2 duty........................... 314 figure 13.3 lcd ram map (1/4 duty) ............................................................................... 315 figure 13.4 lcd ram map (1/3 duty) ............................................................................... 316 figure 13.5 lcd ram map (1/2 duty) ............................................................................... 316 figure 13.6 lcd ram map (static mode) .......................................................................... 317 figure 13.7 output waveforms for each duty cycle (a waveform)................................... 318 figure 13.8 output waveforms for each duty cycle (b waveform)................................... 319 figure 13.9 connection of external split-resistance............................................................ 321 section 14 power-on reset and low-voltage detection circuits (h8/38104 group only) figure 14.1 block diagram of power-on reset circuit and low-voltage detection circuit324 figure 14.2 operational timing of power-on reset circuit ................................................ 328 figure 14.3 operational timing of lvdr circuit................................................................ 329 figure 14.4 operational timing of lvdi circuit ................................................................. 330 figure 14.5 operational timing of low-voltage detection interrupt circuit (using pins vref, extd, and extu) ..................................................................... 331 figure 14.6 lvd function usage example employing pins vref, extd, and extu ............. 332 figure 14.7 timing for operation/release of low-voltage detection circuit..................... 334 section 15 power supply circuit (h8/38104 group only) figure 15.1 power supply connection when internal step-down circuit is used............... 335 figure 15.2 power supply connection when internal step-down circuit is not used........ 336 section 17 electrical characteristics figure 17.1 clock input timing............................................................................................ 408 figure 17.2 res low width timing .................................................................................... 408 figure 17.3 input timing ...................................................................................................... 408 figure 17.4 sck3 input clock timing ................................................................................. 409 figure 17.5 sci3 input/output timing in clocked synchronous mode............................... 409 figure 17.6 output load circuit ........................................................................................... 409 figure 17.7 resonator equivalent circuit ............................................................................. 410
rev. 4.00, 03/04, page xlvi of l figure 17.8 resonator equivalent circuit ............................................................................. 410 appendices figure b.1(a) port 3 block diagram (pins p37 and p36)......................................................... 433 figure b.1(b) port 3 block diagram (pin p35) ........................................................................ 434 figure b.1(c) port 3 block diagram (pins p34 and p33)......................................................... 434 figure b.1(d) port 3 block diagram (pins p32 and p31)......................................................... 435 figure b.2(a) port 4 block diagram (pin p43) ........................................................................ 435 figure b.2(b) port 4 block diagram (pin p42) ........................................................................ 436 figure b.2(c) port 4 block diagram (pin p41) ........................................................................ 437 figure b.2(d) port 4 block diagram (pin p40) ........................................................................ 438 figure b.3 port 5 block diagram ........................................................................................ 439 figure b.4 port 6 block diagram ........................................................................................ 440 figure b.5 port 7 block diagram ........................................................................................ 441 figure b.6 port 8 block diagram (pin p80) ........................................................................ 442 figure b.7(a) port 9 block diagram (pins p91 and p90)......................................................... 442 figure b.7(b) port 9 block diagram (pins p95 to p92) ........................................................... 443 figure b.8 port a block diagram ....................................................................................... 443 figure b.9 port b block diagram........................................................................................ 444 figure e.1 package dimensions (fp-64a).......................................................................... 451 figure e.2 package dimensions (fp-64e) .......................................................................... 452 figure e.3 package dimensions (dp-64s).......................................................................... 453 figure f.1 cross-sectional view of chip (hcd6433802, hcd6433801, and hcd6433800)............................................................................................. 454 figure f.2 cross-sectional view of chip (hcd64338004, hcd64338003, hcd64338002, hcd64338001, and hcd64338000) ...................................... 454 figure f.3 cross-sectional view of chip (hcd64f38004 and hcd64f38002) ............... 455 figure g.1 bonding pad form (hcd6433802, hcd6433801, hcd6433800, hcd64338004, hcd64338003, hcd64338002, hcd64338001, hcd64338000, hcd64f38004, and hcd64f38002)...................................... 456 figure h.1 chip tray specifications (hcd6433802, hcd6433801, and hcd6433800) .. 457 figure h.2 chip tray specifications (hcd64338004, hcd64338003, hcd64338002, hcd64338001, and hcd64338000)................................................................. 458 figure h.3 chip tray specifications (hcd64f38004 and hcd64f38002) ....................... 459
rev. 4.00, 03/04, page xlvii of l tables section 1 overview table 1.1 pad coordinate of hcd6433802, hcd6433801, and hcd6433800 .................... 11 table 1.2 pad coordinate of hcd64338004, hcd64338003, hcd64338002, hcd64338001, and hcd64338000 ...................................................................... 14 table 1.3 pad coordinate of hcd64f38004 and hcd64f38002 ......................................... 17 table 1.4 pin functions.......................................................................................................... 1 9 section 2 cpu table 2.1 instruction set ........................................................................................................ 3 8 table 2.2 operation notation................................................................................................. 39 table 2.3 data transfer instructions ...................................................................................... 40 table 2.4 arithmetic operations instructions ........................................................................ 42 table 2.5 logic operations instructions ................................................................................ 43 table 2.6 shift instructions .................................................................................................... 43 table 2.7 bit manipulation instructions (1) ........................................................................... 45 table 2.7 bit manipulation instructions (2) ........................................................................... 46 table 2.8 branch instructions................................................................................................. 48 table 2.9 system control instructions ................................................................................... 50 table 2.10 block data transfer instructions............................................................................ 51 table 2.11 addressing modes.................................................................................................. 52 table 2.12 effective address calculation................................................................................ 55 table 2.13 registers with shared addresses............................................................................ 68 table 2.14 registers with write-only bits .............................................................................. 68 section 3 exception handling table 3.1 exception sources and vector address.................................................................. 71 table 3.2 interrupt wait states............................................................................................... 81 table 3.3 conditions under which interrupt request flag is set to 1 .................................... 83 section 4 clock pulse generators table 4.1 crystal resonator parameters................................................................................. 91 table 4.2 system clock oscillator and on-chip oscillator selection methods .................... 93 section 5 power-down modes table 5.1(1) operating frequency and waiting time (h8/3802 group, h8/38004 group) ...... 103 table 5.1(2) operating frequency and waiting time (h8/38104 group).................................. 103 table 5.2 transition mode after sleep instruction execution and interrupt handling........ 108 table 5.3 internal state in each operating mode .................................................................. 109
rev. 4.00, 03/04, page xlviii of l section 6 rom table 6.1 setting to prom mode.......................................................................................... 120 table 6.2 mode selection in prom mode (h8/3802) .......................................................... 123 table 6.3 dc characteristics.................................................................................................. 125 table 6.4 ac characteristics.................................................................................................. 126 table 6.5 setting programming modes.................................................................................. 136 table 6.6 boot mode operation............................................................................................. 138 table 6.7 oscillation frequencies for which automatic adjustment of lsi bit rate is possible (f osc ) ........................................................................................................ 139 table 6.8 reprogram data computation table ..................................................................... 143 table 6.9 additional-program data computation table ....................................................... 143 table 6.10 programming time ................................................................................................ 143 table 6.11 command sequence in programmer mode............................................................ 147 table 6.12 ac characteristics in transition to memory read mode ...................................... 150 table 6.13 ac characteristics in transition from memory read mode to another mode ..... 151 table 6.14 ac characteristics in memory read mode ........................................................... 151 table 6.15 ac characteristics in auto-program mode ........................................................... 153 table 6.16 ac characteristics in auto-erase mode ................................................................ 155 table 6.17 ac characteristics in status read mode ............................................................... 156 table 6.18 return codes in status read mode........................................................................ 157 table 6.19 status polling output ............................................................................................. 157 table 6.20 stipulated transition times to command wait state ............................................ 158 table 6.21 flash memory operating states ............................................................................. 159 section 8 i/o ports table 8.1 port functions ........................................................................................................ 16 3 section 9 timers table 9.1 timer functions ..................................................................................................... 198 table 9.2 timer a operating states....................................................................................... 202 table 9.3 pin configuration ................................................................................................... 204 table 9.4 timer f operating states ....................................................................................... 214 table 9.5 pin configuration ................................................................................................... 220 table 9.6 examples of event counter pwm operation ........................................................ 231 table 9.7 operating states of asynchronous event counter ................................................. 232 table 9.8(1) operating states of watchdog timer (h8/38004 group) ...................................... 239 table 9.8(2) operating states of watchdog timer (h8/38104 group) ...................................... 239 section 10 serial communication interface 3 (sci3) table 10.1 pin configuration ................................................................................................... 243 table 10.2 examples of brr settings for various bit rates (asynchronous mode) (1)........ 251 table 10.2 examples of brr settings for various bit rates (asynchronous mode) (2)........ 252 table 10.3 relation between n and clock................................................................................ 252
rev. 4.00, 03/04, page xlix of l table 10.4 maximum bit rate for each frequency (asynchronous mode)............................ 253 table 10.5 brr settings for various bit rates (clocked synchronous mode) (1)................. 253 table 10.5 brr settings for various bit rates (clocked synchronous mode) (2)................. 254 table 10.6 relation between n and clock................................................................................ 255 table 10.7 data transfer formats (asynchronous mode) ....................................................... 258 table 10.8 smr settings and corresponding data transfer formats ..................................... 259 table 10.9 smr and scr3 settings and clock source selection ........................................... 260 table 10.10 ssr status flags and receive data handling........................................................ 265 table 10.11 sci3 interrupt requests ......................................................................................... 280 table 10.12 transmit/receive interrupts ................................................................................... 281 section 11 10-bit pwm table 11.1 pin configuration ................................................................................................... 288 table 11.2 pwm operating states........................................................................................... 292 section 12 a/d converter table 12.1 pin configuration ................................................................................................... 295 table 12.2 operating states of a/d converter ........................................................................ 297 section 13 lcd controller/driver table 13.1 pin configuration ................................................................................................... 308 table 13.2 duty cycle and common function selection ........................................................ 310 table 13.3 segment driver selection....................................................................................... 310 table 13.4 frame frequency selection .................................................................................... 312 table 13.5 output levels ......................................................................................................... 3 20 table 13.6 power-down modes and display operation.......................................................... 321 section 14 power-on reset and low-voltage detection circuits (h8/38104 group only) table 14.1 lvdcr settings and select functions .................................................................. 326 section 17 electrical characteristics table 17.1 absolute maximum ratings................................................................................... 347 table 17.2 dc characteristics (1) ............................................................................................ 351 table 17.2 dc characteristics (2) ............................................................................................ 352 table 17.2 dc characteristics (3) ............................................................................................ 353 table 17.2 dc characteristics (4) ............................................................................................ 354 table 17.2 dc characteristics (5) ............................................................................................ 355 table 17.2 dc characteristics (6) ............................................................................................ 356 table 17.3 control signal timing............................................................................................ 358 table 17.4 serial interface (sci3) timing............................................................................... 360 table 17.5 a/d converter characteristics ............................................................................... 360 table 17.6 lcd characteristics ............................................................................................... 362 table 17.7 absolute maximum ratings................................................................................... 363
rev. 4.00, 03/04, page l of l table 17.8 dc characteristics.................................................................................................. 368 table 17.9 control signal timing............................................................................................ 375 table 17.10 serial interface (sci3) timing............................................................................... 378 table 17.11 a/d converter characteristics ............................................................................... 379 table 17.12 lcd characteristics ............................................................................................... 381 table 17.13 flash memory characteristics................................................................................ 382 table 17.14 absolute maximum ratings................................................................................... 384 table 17.15 dc characteristics (1)............................................................................................ 389 table 17.15 dc characteristics (2)............................................................................................ 390 table 17.15 dc characteristics (3)............................................................................................ 391 table 17.15 dc characteristics (4)............................................................................................ 392 table 17.15 dc characteristics (5)............................................................................................ 393 table 17.16 control signal timing............................................................................................ 398 table 17.17 serial interface (sci3) timing............................................................................... 399 table 17.18 a/d converter characteristics ............................................................................... 400 table 17.19 lcd characteristics ............................................................................................... 401 table 17.20 flash memory characteristics................................................................................ 402 table 17.21 power supply voltage detection circuit characteristics (1) ................................. 404 table 17.22 power supply voltage detection circuit characteristics (2) ................................. 404 table 17.23 power supply voltage detection circuit characteristics (3) ................................. 405 table 17.24 power supply voltage detection circuit characteristics (4) ................................. 406 table 17.25 power supply voltage detection circuit characteristics (5) ................................. 407 table 17.26 power-on reset circuit characteristics................................................................. 407 table 17.27 watchdog timer characteristics ............................................................................ 408 appendices table a.1 instruction set ........................................................................................................ 4 15 table a.2 operation code map .............................................................................................. 425 table a.3 number of states required for execution.............................................................. 427 table a.4 number of cycles in each instruction ................................................................... 427 table c.1 port states ............................................................................................................. . 445 table d.1 product code lineup of h8/3802 group ............................................................... 446 table d.2 product code lineup of h8/38004 group ............................................................. 447 table d.3 product code lineup of h8/38104 group ............................................................. 449
rev. 4.00, 03/04, page 1 of 462 section 1 overview 1.1 features ? high-speed h8/300l central processing unit complete instruction set compatibility with h8/300 cpu sixteen 8-bit general registers (can be used as eight 16-bit general registers) 55 basic instructions ? various peripheral functions timer a (can be used as a time base for a clock) timer f (16-bit timer) asynchronous event counter (16-bit timer) watchdog timer (wdt) (h8/38004 group and h8/38104 group only) sci3 (asynchronous or clocked synchronous serial communication interface) 10-bit pwm 10-bit a/d converter lcd controller/driver power-on reset and low-voltage detect circuits (h8/38104 group only)
rev. 4.00, 03/04, page 2 of 462 ? on-chip memory product classification model rom ram h8/38004 hd64f38004 32 kbytes 1 kbyte flash memory version (f-ztat tm version * 1 ) h8/38002 hd64f38002 16 kbytes 1 kbyte h8/38104 hd64f38104 32 kbytes 1 kbyte h8/38102 hd64f38102 16 kbytes 1 kbyte prom version (ztat tm version * 2 ) h8/3802 hd6473802 16 kbytes 1 kbyte h8/3802 hd6433802 16 kbytes 1 kbyte h8/3801 hd6433801 12 kbytes 512 bytes h8/3800 hd6433800 8 kbytes 512 bytes h8/38004 hd64338004 32 kbytes 1 kbyte h8/38003 hd64338003 24 kbytes 1 kbyte h8/38002 hd64338002 16 kbytes 1 kbyte h8/38001 hd64338001 12 kbytes 512 bytes mask rom version h8/38000 hd64338000 8 kbytes 512 bytes h8/38104 hd64338104 32 kbytes 1 kbyte h8/38103 hd64338103 24 kbytes 1 kbyte h8/38102 hd64338102 16 kbytes 1 kbyte h8/38101 hd64338101 12 kbytes 512 bytes h8/38100 hd64338100 8 kbytes 512 bytes notes: 1. f-ztat is a trademark of renesas technology corp. 2. ztat is a trademark of renesas technology corp. ? general i/o ports i/o pins: 39 i/o pins input-only pins: 5 input pins output-only pins: 6 output pins (5 pins on h8/38104 group) ? supports various power-down modes
rev. 4.00, 03/04, page 3 of 462 ? compact package package code body size pin pitch qfp-64 fp-64a 14.0 14.0 mm 0.8 mm lqfp-64 fp-64e 10.0 10.0 mm 0.5 mm dp-64s dp-64s 17.0 57.6 mm 1.0 mm die ??? the dp-64s package is only for the h8/3802 group. the chip is not supported by the h8/38104 group.
rev. 4.00, 03/04, page 4 of 462 1.2 internal block diagram subclock oscillator h8/300l cpu ram system clock oscillator lcd power supply port 3 port a port 9 port 8 port 7 port b port 4 port 5 port 6 rom timer a timer f asynchronous event counter (aec) sci3 10-bit pwm1 10-bit a/d converter 10-bit pwm2 lcd controller/driver large-current (25 ma/pin) high-voltage open-drain pin (7 v) large-current (10 ma/pin) high-voltage open-drain pin (7 v) high-voltage (7 v) input pin vss = avss vcc test pa3/com4 pa2/com3 pa1/com2 pa0/com1 p80/seg25 p77/seg24 p76/seg23 p75/seg22 p74/seg21 p73/seg20 p72/seg19 p71/seg18 p70/seg17 p60/seg9 p61/seg10 p62/seg11 p63/seg12 p64/seg13 p65/seg14 p66/seg15 p67/seg16 p40/sck32 p41/rxd32 p42/txd32 p43/ osc1 osc2 x1 x2 p31/tmofl p32/tmofh p33 p34 p35 p36/aevh p37/aevl p50/ /seg1 p51/ /seg2 p52/ /seg3 p53/ /seg4 p54/ /seg5 p55/ /seg6 p56/ /seg7 p57/ /seg8 pb3/an3/ pb2/an2 pb1/an1 pb0/an0 v1 v2 v3 avcc irqaec vss p95 p94 p93 p92 p91/pwm2 p90/pwm1 figure 1.1 internal block diagram of h8/3802 group
rev. 4.00, 03/04, page 5 of 462 h8/300l cpu ram rom sci3 wdt vss = avss vcc test pa3/com4 pa2/com3 pa1/com2 pa0/com1 p80/seg25 p77/seg24 p76/seg23 p75/seg22 p74/seg21 p73/seg20 p72/seg19 p71/seg18 p70/seg17 p60/seg9 p61/seg10 p62/seg11 p63/seg12 p64/seg13 p65/seg14 p66/seg15 p67/seg16 p40/sck32 p41/rxd32 p42/txd32 p43/ osc1 osc2 x1 x2 p31/tmofl p32/tmofh p33 p34 p35 p36/aevh p37/aevl p50/ /seg1 p51/ /seg2 p52/ /seg3 p53/ /seg4 p54/ /seg5 p55/ /seg6 p56/ /seg7 p57/ /seg8 pb3/an3/ pb2/an2 pb1/an1 pb0/an0 v1 v2 v3 avcc note: when the on-chip emulator is used, pins p95, p33, p34, and p35 are unavailable to the user because they are used exclusively by the on-chip emulator. irqaec vss p95 p94 p93 p92 p91/pwm2 p90/pwm1 subclock oscillator system clock oscillator timer a timer f asynchronous event counter (aec) 10-bit pwm1 10-bit pwm2 lcd controller/driver 10-bit a/d converter lcd power supply port 3 port a port 9 port 8 port 7 port b port 4 port 5 port 6 figure 1.2 internal block diagram of h8/38004 group
rev. 4.00, 03/04, page 6 of 462 h8/300l cpu ram rom sci3 power-on reset and low-voltage detection circuit wdt cvcc vss = avss vcc res test pa3/com4 pa2/com3 pa1/com2 pa0/com1 p80/seg25 p77/seg24 p76/seg23 p75/seg22 p74/seg21 p73/seg20 p72/seg19 p71/seg18 p70/seg17 p60/seg9 p61/seg10 p62/seg11 p63/seg12 p64/seg13 p65/seg14 p66/seg15 p67/seg16 p40/sck32 p41/rxd32 p42/txd32 p43/ irq0 osc1 osc2 x1 x2 p31/tmofl p32/tmofh p33 p34 p35 p36/aevh p37/aevl p50/ wkp0 /seg1 p51/ wkp1 /seg2 p52/ wkp2 /seg3 p53/ wkp3 /seg4 p54/ wkp4 /seg5 p55/ wkp5 /seg6 p56/ wkp6 /seg7 p57/ wkp7 /seg8 pb3/an3/ irq 1 pb2/an2 pb1/an1/extu pb0/an0/extd v1 v2 v3 avcc note: when the on-chip emulator is used, pins p95, p33, p34, and p35 are unavailable to the user because they are used exclusively by the on-chip emulator. irqaec vss p95 p93/vref p92 p91/pwm2 p90/pwm1 subclock oscillator system clock oscillator timer a timer f asynchronous event counter (aec) 10-bit pwm1 10-bit pwm2 lcd controller/driver 10-bit a/d converter lcd power supply port 3 port a port 9 port 8 port 7 port b port 4 port 5 port 6 : large current (15 ma) pin figure 1.3 internal block diagram of h8/38104 group
rev. 4.00, 03/04, page 7 of 462 1.3 pin arrangement p90/pwm1 p91/pwm2 p92 p93 p94 p95 vss irqaec p40/sck32 p41/rxd32 p42/txd32 p43/ avcc pb0/an0 pb1/an1 pb2/an2 pb3/ /an3 x1 x2 vss=avss osc2 osc1 test p31/tmofl p32/tmofh p33 p34 p35 p36/aevh p37/aevl vcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 p70/seg17 p71/seg18 p72/seg19 p73/seg20 p74/seg21 p75/seg22 p76/seg23 p77/seg24 p80/seg25 pa0/com1 pa1/com2 pa2/com3 pa3/com4 v3 v2 v1 p50/ /seg1 p51/ /seg2 p52/ /seg3 p53/ /seg4 p54/ /seg5 p55/ /seg6 p56/ /seg7 p57/ /seg8 p60/seg9 p61/seg10 p62/seg11 p63/seg12 p64/seg13 p65/seg14 p66/seg15 p67/seg16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 fp-64a, fp-64e (top view) note: when the on-chip emulator is used, pins p95, p33, p34, and p35 are unavailable to the user because they are used exclusively by the on-chip emulator. 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 figure 1.4 pin arrangement of h8/3802 and h8/38004 group (fp-64a, fp-64e)
rev. 4.00, 03/04, page 8 of 462 p40/sck32 p41/rxd32 p42/txd32 p43/ avcc pb0/an0 pb1/an1 pb2/an2 pb3/ /an3 x1 x2 vss=avss osc2 osc1 test p31/tmofl p32/tmofh p33 p34 p35 p36/aevh p37/aevl vcc v1 v2 v3 pa3/com4 pa2/com3 pa1/com2 pa0/com1 p80/seg25 irqaec vss p95 p94 p93 p92 p91/pwm2 p90/pwm1 p50/ /seg1 p51/ /seg2 p52/ /seg3 p53/ /seg4 p54/ /seg5 p55/ /seg6 p56/ /seg7 p57/ /seg8 p60/seg9 p61/seg10 p62/seg11 p63/seg12 p64/seg13 p65/seg14 p66/seg15 p67/seg16 p70/seg17 p71/seg18 p72/seg19 p73/seg20 p74/seg21 p75/seg22 p76/seg23 p77/seg24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 dp-64s (top view) figure 1.5 pin arrangement of h8/3802 group (dp-64s)
rev. 4.00, 03/04, page 9 of 462 p90/pwm1 p91/pwm2 p92 p93/vref cvcc p95 vss irqaec p40/sck32 p41/rxd32 p42/txd32 p43/ irq0 avcc pb0/an0/extd pb1/an1/extu pb2/an2 pb3/ irq1 /an3 x1 x2 vss=avss osc2 osc1 test res p31/tmofl p32/tmofh p33 p34 p35 p36/aevh p37/aevl vcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 p70/seg17 p71/seg18 p72/seg19 p73/seg20 p74/seg21 p75/seg22 p76/seg23 p77/seg24 p80/seg25 pa0/com1 pa1/com2 pa2/com3 pa3/com4 v3 v2 v1 p50/ wkp0 /seg1 p51/ wkp1 /seg2 p52/ wkp2 /seg3 p53/ wkp3 /seg4 p54/ wkp4 /seg5 p55/ wkp5 /seg6 p56/ wkp6 /seg7 p57/ wkp7 /seg8 p60/seg9 p61/seg10 p62/seg11 p63/seg12 p64/seg13 p65/seg14 p66/seg15 p67/seg16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 fp-64a, fp-64e (top view) note: when the on-chip emulator is used, pins p95, p33, p34, and p35 are unavailable to the user because they are used exclusively by the on-chip emulator. 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 figure 1.6 pin arrangement of h8/38104 group (fp-64a, fp-64e)
rev. 4.00, 03/04, page 10 of 462 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 30 31 32 33 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 x y (0, 0) model name chip size: 3.60 mm 3.73 mm voltage level on the back of the chip: gnd figure 1.7 pad arrangement of hcd6433802, hcd6433801, and hcd6433800 (top view)
rev. 4.00, 03/04, page 11 of 462 table 1.1 pad coordinate of hcd6433802, hcd6433801, and hcd6433800 coordinate coordinate pad no. pad name x ( 1 pb3/ irq1 /an3 -1677 1495 32 p71/seg18 1400 -1742 2 x1 -1677 1084 33 p70/seg17 1578 -1742 3 x2 -1677 943 34 p67/seg16 1677 -1401 4 avss -1677 765 35 p66/seg15 1677 -1190 5 vss -1677 619 36 p65/seg14 1677 -950 6 osc2 -1677 488 37 p64/seg13 1677 -801 7 osc1 -1677 356 38 p63/seg12 1677 -608 8 test -1677 225 39 p62/seg11 1677 -459 9 res -1677 94 40 p61/seg10 1677 -310 10 p31/tmofl -1677 -40 41 p60/seg9 1677 -160 11 p32/tmofh -1677 -176 42 p57/ wkp7 /seg8 1677 -11 12 p33 -1677 -313 43 p56/ wkp6 /seg7 1677 121 13 p34 -1677 -450 44 p55/ wkp5 /seg6 1677 252 14 p35 -1677 -587 45 p54/ wkp4 /seg5 1677 383 15 p36/aevh -1677 -943 46 p53/ wkp3 /seg4 1677 801 16 p37/aevl -1677 -1083 47 p52/ wkp2 /seg3 1677 950 17 vcc -1677 -1404 48 p51/ wkp1 /seg2 1677 1190 18 v1 -1578 -1742 49 p50/ wkp0 /seg1 1677 1402 19 v2 -1339 -1742 50 p90/pwm1 1578 1742 20 v3 -1193 -1742 51 p91/pwm2 1411 1742 21 pa3/com4 -1049 -1742 52 p92 1193 1742 22 pa2/com3 -850 -1742 53 p93 1051 1742 23 pa1/com2 -400 -1742 54 p94 850 1742 24 pa0/com1 -200 -1742 55 p95 650 1742 25 p80/seg25 0 -1742 56 vss 400 1742 26 p77/seg24 320 -1742 57 irqaec 200 1742 27 p76/seg23 451 -1742 58 p40/sck32 -298 1742 28 p75/seg22 583 -1742 59 p41/rxd32 -435 1742 29 p74/seg21 850 -1742 60 p42/txd32 -572 1742 30 p73/seg20 1051 -1742 61 p43/ irq0 -752 1742 31 p72/seg19 1193 -1742 62 avcc -1036 1742
rev. 4.00, 03/04, page 12 of 462 coordinate coordinate pad no. pad name x ( 63 pb0/an0 -1170 1742 65 pb2/an2 -1578 1742 64 pb1/an1 -1400 1742 note: the power supply (vss) pads in pad numbers 4, 5, and 56 must not be open but connected. the test pad in pad number 8 must be connected to the vss voltage level. if not, this lsi does not operate correctly. the coordinate values indicate center positions of pads and the accuracy is 5 m. the home-point position is center of the chip and the center is located at half the distance between the upper and lower pads and left and right pads.
rev. 4.00, 03/04, page 13 of 462 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 x (0, 0) model name y chip size: 2.73 mm 3.27 mm voltage level on the back of the chip: gnd : nc pad figure 1.8 pad arrangement of hcd64338004, hcd64338003, hcd64338002, hcd64338001, and hcd64338000 (top view)
rev. 4.00, 03/04, page 14 of 462 table 1.2 pad coordinate of hcd64338004, hcd64338003, hcd64338002, hcd64338001, and hcd64338000 coordinate coordinate pad no. pad name x ( 1 pb3/ irq1 /an3 -1224 1214 32 p70/seg17 913 -1484 2 x1 -1224 957 33 p67/seg16 1215 -1194 3 x2 -1224 786 34 p66/seg15 1215 -1080 4 vss = avss -1224 596 35 p65/seg14 1215 -909 5 osc2 -1224 406 36 p64/seg13 1215 -738 6 osc1 -1224 234 37 p63/seg12 1215 -566 7 test -1224 120 38 p62/seg11 1215 -395 8 res -1224 6 39 p61/seg10 1215 -224 9 p31/tmofl -1224 -108 40 p60/seg9 1215 -52 10 p32/tmofh -1224 -222 41 p57/ wkp7 /seg8 1215 119 11 p33 -1224 -336 42 p56/ wkp6 /seg7 1215 233 12 p34 -1224 -450 43 p55/ wkp5 /seg6 1215 404 13 p35 -1224 -564 44 p54/ wkp4 /seg5 1215 576 14 p36/aevh -1224 -678 45 p53/ wkp3 /seg4 1215 747 15 p37/aevl -1224 -849 46 p52/ wkp2 /seg3 1215 919 16 vcc -1224 -1142 47 p51/ wkp1 /seg2 1215 1090 17 v1 -922 -1484 48 p50/ wkp0 /seg1 1215 1206 18 v2 -799 -1484 49 p90/pwm1 913 1494 19 v3 -676 -1484 50 p91/pwm2 790 1494 20 pa3/com4 -553 -1484 51 p92 667 1494 21 pa2/com3 -430 -1484 52 p93 544 1494 22 pa1/com2 -307 -1484 53 p94 421 1494 23 pa0/com1 -185 -1484 54 p95 299 1494 24 p80/seg25 -62 -1484 55 vss 176 1494 25 p77/seg24 53 -1484 56 irqaec 37 1494 26 p76/seg23 176 -1484 57 p40/sck32 -77 1494 27 p75/seg22 299 -1484 58 p41/rxd32 -200 1494 28 p74/seg21 421 -1484 59 p42/txd32 -323 1494 29 p73/seg20 544 -1484 60 p43/ irq0 -446 1494 30 p72/seg19 667 -1484 61 avcc -569 1494 31 p71/seg18 790 -1484 62 pb0/an0 -692 1494
rev. 4.00, 03/04, page 15 of 462 coordinate coordinate pad no. pad name x ( 63 pb1/an1 -815 1494 64 pb2/an2 -937 1494 note: the power supply (vss) pads in pad numbers 4 and 55 must not be open but connected. the test pad in pad number 7 must be connected to the vss voltage level. if not, this lsi does not operate correctly. the coordinate values indicate center positions of pads and the accuracy is 5 m. the home-point position is center of the chip and the center is located at half the distance between the upper and lower pads and left and right pads.
rev. 4.00, 03/04, page 16 of 462 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 x y model name (0, 0) hcd64f38004 hcd64f38004c4 hcd64f38002 hcd64f38002c4 hd64f38004 product model name model name on chip hd64f38004-4 hd64f38004 hd64f38004-4 chip size: 4.09 mm 3.82 mm voltage level on the back of the chip: gnd : nc pad figure 1.9 pad arrangement of hcd64f38004 and hcd64f38002 (top view)
rev. 4.00, 03/04, page 17 of 462 table 1.3 pad coordinate of hcd64f38004 and hcd64f38002 coordinate coordinate pad no. pad name x ( 1 pb3/ irq1 /an3 -1915 1490 32 p71/seg18 1411 -1779 2 x1 -1915 1182 33 p70/seg17 1628 -1779 3 x2 -1915 1022 34 p67/seg16 1914 -1496 4 vss -1915 926 35 p66/seg15 1914 -1297 5 vss = avss -1915 786 36 p65/seg14 1914 -1098 6 osc2 -1915 648 37 p64/seg13 1914 -899 7 osc1 -1915 495 38 p63/seg12 1914 -700 8 test -1915 295 39 p62/seg11 1914 -500 9 res -1915 96 40 p61/seg10 1914 -302 10 p31/tmofl -1915 -103 41 p60/seg9 1914 -103 11 p32/tmofh -1915 -302 42 p57/ wkp7 /seg8 1914 96 12 p33 -1915 -486 43 p56/ wkp6 /seg7 1914 295 13 p34 -1915 -657 44 p55/ wkp5 /seg6 1914 495 14 p35 -1915 -750 45 p54/ wkp4 /seg5 1914 694 15 p36/aevh -1915 -989 46 p53/ wkp3 /seg4 1914 893 16 p37/aevl -1915 -1247 47 p52/ wkp2 /seg3 1914 1092 17 vcc -1915 -1438 48 p51/ wkp1 /seg2 1914 1291 18 v1 -1623 -1779 49 p50/ wkp0 /seg1 1914 1490 19 v2 -1406 -1779 50 p90/pwm1 1628 1779 20 v3 -1189 -1779 51 p91/pwm2 1368 1779 21 pa3/com4 -973 -1779 52 p92 1113 1779 22 pa2/com3 -756 -1779 53 p93 976 1779 23 pa1/com2 -539 -1779 54 p94 759 1779 24 pa0/com1 -323 -1779 55 p95 542 1779 25 p80/seg25 -106 -1779 56 vss 324 1779 26 p77/seg24 111 -1779 57 irqaec 96 1779 27 p76/seg23 328 -1779 58 p40/sck32 -109 1779 28 p75/seg22 544 -1779 59 p41/rxd32 -327 1779 29 p74/seg21 761 -1779 60 p42/txd32 -545 1779 30 p73/seg20 978 -1779 61 p43/ irq0 -762 1779 31 p72/seg19 1194 -1779 62 avcc -980 1779
rev. 4.00, 03/04, page 18 of 462 coordinate coordinate pad no. pad name x ( 63 pb0/an0 -1198 1779 65 pb2/an2 -1613 1779 64 pb1/an1 -1414 1779 note: the power supply (vss) pads in pad numbers 4, 5, and 56 must not be open but connected. the test pad in pad number 8 must be connected to the vss voltage level. if not, this lsi does not operate correctly. the coordinate values indicate center positions of pads and the accuracy is 5 m. the home-point position is center of the chip and the center is located at half the distance between the upper and lower pads and left and right pads.
rev. 4.00, 03/04, page 19 of 462 1.4 pin functions table 1.4 pin functions pin no. type symbol fp-64a, fp-64e dp-64s pad no. * 1 * 3 pad no. * 2 i/o functions v cc 16 24 17 16 input power supply pin. connect this pin to the system power supply. power source pins v ss 4(=av ss ) 55 12 (= av ss ) 63 4 5 56 4 55 input ground pin. connect this pin to the system power supply (0v). av cc 61 5 62 61 input analog power supply pin for the a/d converter. when the a/d converter is not used, connect this pin to the system power supply. av ss 4(=v ss )12(=v ss )4 5 4 input ground pin for the a/d converter. connect this pin to the system power supply (0 v). v1 v2 v3 17 18 19 25 26 27 18 19 20 17 18 19 input power supply pin for the lcd controller/driver. cv cc * 4 53 ? ? ? input this is the internal step-down power supply pin. to ensure stability, a capacitor with a rating of about 0.1 f should be connected between this pin and the v ss pin. clock pins osc1 6 14 7 6 input osc2 5 13 6 5 output these pins connect to a crystal or ceramic resonator for system clocks, or can be used to input an external clock. see section 4, clock pulse generators, for a typical connection. x1 2 10 2 2 input x2 3 11 3 3 output these pins connect to a 32.768- or 38.4-khz crystal resonator for subclocks. see section 4, clock pulse generators, for a typical connection.
rev. 4.00, 03/04, page 20 of 462 pin no. type symbol fp-64a, fp-64e dp-64s pad no. * 1 * 3 pad no. * 2 i/o functions res 8 16 9 8 input reset pin. when this driven low, thechipisreset. system control test 7 15 88 7 input test pin. connect this pin to v ss . users cannot use this pin. irq0 60 4 61 60 interrupt pins irq1 19 11 input external interrupt request input pins. can select the rising or falling edge. irqaec 56 64 57 56 input asynchronous event counter interrupt input pin. enables asynchronous event input. on the h8/38104 group, this must be fixed at v cc or gnd because the oscillator is selected by the input level during resets. refer to section 4, clock pulse generators, for information on the selection method. wkp7 to wkp0 41 to 48 49 to 56 42 to 49 41 to 48 input wakeup interrupt request input pins. can select the rising or falling edge. timer aevl aevh 15 14 23 22 16 15 15 14 input this is an event input pin for input to the asynchronous event counter. tmofl 9 17 10 9 output this is an output pin for waveforms generated by the timer fl output compare function. tmofh 10 18 11 10 output this is an output pin for waveforms generated by the timer fh output compare function. pwm1 49 57 50 49 10-bit pwm pwm2 50 58 51 50 output these are output pins for waveforms generated by the channel 1 and 2 10-bit pwms.
rev. 4.00, 03/04, page 21 of 462 pin no. type symbol fp-64a, fp-64e dp-64s pad no. * 1 * 3 pad no. * 2 i/o functions i/o ports p37 to p31 15 to 9 23 to 17 16 to 10 15 to 9 i/o 7-bit i/o port. input or output can be designated for each bit by means of the port control register 3 (pcr3). when the on- chip emulator is used, pins p33, p34, and p35 are unavailable to the user because they are used exclusively by the on-chip emulator. p43 60 4 61 60 input 1-bit input port. p42 to p40 59 to 57 3 to 1 60 to 58 59 to 57 i/o 3-bit i/o port. input or output can be designated for each bit by means of the port control register 4 (pcr4). p57 to p50 41 to 48 49 to 56 42 to 49 41 to 48 i/o 8-bit i/o port. input or output can be designated for each bit by means of the port control register 5 (pcr5). p67 to p60 33 to 40 41 to 48 34 to 41 33 to 40 i/o 8-bit i/o port. input or output can be designated for each bit by means of the port control register 6 (pcr6). p77 to p70 25 to 32 33 to 40 26 to 33 25 to 32 i/o 8-bit i/o port. input or output can be designated for each bit by means of the port control register 7 (pcr7). p80 24 32 25 24 i/o 1-bit i/o port. input or output can be designated for each bit by means of the port control register 8 (pcr8). p95 to p90 54 to 49 62 to 57 55 to 50 54 to 49 output 6-bit output port. when the on- chip emulator is used, pin p95 is unavailable to the user because it is used exclusively by the on- chip emulator. in the f-ztat version, pin p95 should not be open but pulled up to go high in user mode. note that the h8/38104 group is not equipped with a pin 94.
rev. 4.00, 03/04, page 22 of 462 pin no. type symbol fp-64a, fp-64e dp-64s pad no. * 1 * 3 pad no. * 2 i/o functions i/o ports pa3 to pa0 20 to 23 28 to 31 21 to 24 20 to 23 i/o 4-bit i/o port. input or output can be designated for each bit by means of the port control register a (pcra). pb3 to pb0 1, 64 to 62 9to6 1, 65 to 63 1, 64 to 62 input 4-bit input port. rxd32 58 2 59 58 input receive data input pin. txd32 59 3 60 59 output transmit data output pin. serial com- munication interface (sci) sck32 57 1 58 57 i/o clock i/o pin. a/d converter an3 to an0 1, 64 to 62 9to6 1, 65 to 63 1, 64 to 62 input analog data input pins. com4 to com1 20 to 23 28 to 31 21 to 24 20 to 23 output lcd common output pins. lcd controller/ driver seg25 to seg1 24 to 48 32 to 56 25 to 49 24 to 48 output lcd segment output pins. vref 52 ? ? ? input reference voltage input pin. extd 62 ? ? ? input power supply drop detection voltage input pin. low-voltage detection circuit (lvd) * 4 extu 63 ? ? ? input power supply rise detection voltage input pin. notes: 1. pad number for hcd6433802, hcd6433801, and hcd6433800 2. pad number for hcd64338004, hcd64338003, hcd64338002, hcd64338001, and hcd64338000 3. pad number for hcd64f38004 and hcd64f38002 4. h8/38104 group only
cpu30l0a_000020020900 rev. 4.00, 03/04, page 23 of 462 section 2 cpu the h8/300l cpu has sixteen 8-bit general registers, which can also be paired as eight 16-bit registers. its concise instruction set is designed for high-speed operation. 2.1 features ? general-register architecture ? sixteen 8-bit general registers, also usable as eight 16-bit registers ? fifty-five basic instructions ? multiply and divide instructions ? powerful bit-manipulation instructions ? eight addressing modes ? register direct [rn] ? register indirect [@rn] ? register indirect with displacement [@(d:16,rn)] ? register indirect with post-increment or pre-decrement [@rn+ or @?rn] ? absolute address [@aa:8 or @aa:16] ? immediate [#xx:8 or #xx:16] ? program-counter relative [@(d:8,pc)] ? memory indirect [@@aa:8] ? 64-kbyte address space ? high-speed operation ? all frequently-used instructions execute in two to four states ? 8/16-bit register-register add/subtract : 0.25 s * ? 8 8-bit multiply : 1.75 s * ? 16 8-bit divide : 1.75 s * note: * these values are at =8mhz. ? power-down state ? transition to power-down state by sleep instruction
rev. 4.00, 03/04, page 24 of 462 2.2 address space and memory map the address space of this lsi is 64 kbytes, which includes the program area and the data area. figures 2.1 show the memory map. h'0000 h'0029 h'002a h'3fff h'f740 h'f74c h'fb80 h'ff7f h'ff80 h'ffff interrupt vector area (prom and mask rom versions) on-chip rom (16 kbytes) on-chip ram (1 kbyte) internal i/o register (128 bytes) not used not used lcd ram (13 bytes) figure 2.1(1) h8/3802 memory map
rev. 4.00, 03/04, page 25 of 462 h'0000 h'0029 h'002a h'2fff h'f740 h'f74c h'fd80 h'ff7f h'ff80 h'ffff interrupt vector area (mask rom version) on-chip rom (12 kbytes) on-chip ram (512 bytes) internal i/o register (128 bytes) not used not used lcd ram (13 bytes) figure 2.1(2) h8/3801 memory map
rev. 4.00, 03/04, page 26 of 462 h'0000 h'0029 h'002a h'1fff h'f740 h'f74c h'fd80 h'ff7f h'ff80 h'ffff interrupt vector area (mask rom version) on-chip rom (8 kbytes) on-chip ram (512 bytes) internal i/o register (128 bytes) not used not used lcd ram (13 bytes) figure 2.1(3) h8/3800 memory map
rev. 4.00, 03/04, page 27 of 462 h'0000 h'0029 h'002a h'7fff h'7000 h'f020 h'f02b h'f740 h'f74c h'f780 h'fb80 h'fb7f h'ff7f h'ff80 h'ffff interrupt vector area firmware for on-chip emulator * 1 (flash memory version) (mask rom version) on-chip rom (32 kbytes) 1. when the on-chip emulator is used, this area is unavailable to the user. 2. when flash memory is programmed, this area is used by the programming control program. when the on-chip emulator is used, this area is unavailable to the user. note: on-chip ram (2 kbytes) user area (1 kbyte) internal i/o register (128 bytes) internal i/o register not used not used not used work area for flash memory reprogramming * 2 (1 kbyte) lcd ram (13 bytes) h'0000 h'0029 h'002a h'7fff h'f740 h'f74c h'fb80 h'ff7f h'ff80 h'ffff interrupt vector area on-chip rom (32 kbytes) on-chip ram (1 kbyte) internal i/o register (128 bytes) not used not used lcd ram (13 bytes) figure 2.1(4) h8/38004, h8/38104 memory map
rev. 4.00, 03/04, page 28 of 462 h'0000 h'0029 h'002a h'5fff h'f740 h'f74c h'fb80 h'ff7f h'ff80 h'ffff interrupt vector area (mask rom version) on-chip rom (24 kbytes) on-chip ram (1 kbyte) internal i/o register (128 bytes) not used not used lcd ram (13 bytes) figure 2.1(5) h8/38003, h8/38103 memory map
rev. 4.00, 03/04, page 29 of 462 h'0000 interrupt vector area on-chip rom (16 kbytes) not used firmware for on-chip emulator * 1 not used interrupt vector area on-chip rom (16 kbytes) not used internal i/o register not used lcd ram (13 bytes) not used work area for flash memory reprogramming * 2 (1 kbyte) on-chip ram (2 kbytes) user area (1 kbyte) internal i/o register (128 bytes) lcd ram (13 bytes) not used internal i/o register (128 bytes) on-chip ram (1 kbyte) (flash memory version) (mask rom version) h'0029 h'002a h'7fff h'7000 h'3fff h'f020 h'f02b h'f740 h'f74c h'f780 h'fb80 h'fb7f h'ff7f h'ff80 h'ffff 1. when the on-chip emulator is used, this area is unavailable to the user. 2. when flash memory is programmed, this area is used by the programming control program. when the on-chip emulator is used, this area is unavailable to the user. notes: h'3fff h'0000 h'0029 h'002a h'f740 h'f74c h'fb80 h'ff7f h'ff80 h'ffff figure 2.1(6) h8/38002, h8/38102 memory map
rev. 4.00, 03/04, page 30 of 462 h'0000 h'0029 h'002a h'2fff h'f740 h'f74c h'fd80 h'ff7f h'ff80 h'ffff interrupt vector area on-chip rom (12 kbytes) not used lcd ram (13 bytes) not used internal i/o register (128 bytes) on-chip ram (512 bytes) (mask rom version) figure 2.1(7) h8/38001, h8/38101 memory map
rev. 4.00, 03/04, page 31 of 462 h'0000 h'0029 h'002a h'1fff h'f740 h'f74c h'fd80 h'ff7f h'ff80 h'ffff interrupt vector area on-chip rom (8 kbytes) not used lcd ram (13 bytes) not used internal i/o register (128 bytes) on-chip ram (512 bytes) (mask rom version) figure 2.1(8) h8/38000, h8/38100 memory map
rev. 4.00, 03/04, page 32 of 462 2.3 register configuration figure 2.2 shows the internal register configuration of the h8/300l cpu. there are two groups of registers: the general registers and control registers. general registers (rn) control register (cr) [legend] : stack pointer : program counter : condition code register : interrupt mask bit : user bit : half-carry flag : negative flag : zero flag : overflow flag : carry flag sp pc ccr i u h n z v c ccr 70 15 0 70 r0h r1h r2h r3h r4h r5h r6h r7h r0l r1l r2l r3l r4l r5l r6l r7l (sp) pc i uhunzvc 76543210 figure 2.2 cpu registers
rev. 4.00, 03/04, page 33 of 462 2.3.1 general registers all the general registers can be used as both data registers and address registers. when used as data registers, they can be accessed as 16-bit registers (r0 to r7), or the upper bytes (r0h to r7h) and low bytes (r0l to r7l) can be accessed separately as 8-bit registers. when used as address registers, the general registers are accessed as 16-bit registers (r0 to r7). r7 also functions as the stack pointer (sp), used implicitly by hardware in exception handling and subroutine calls. when it functions as the stack pointer, as indicated in figure 2.3, sp (r7) points to the top of the stack. sp (r7) lower address side [h'0000] unused area stack area upper address side [h'ffff] figure 2.3 stack pointer 2.3.2 program counter (pc) this 16-bit counter indicates the address of the next instruction the cpu will execute. all instructions are fetched 16 bits (1 word) at a time, so the least significant bit of the pc is ignored (always regarded as 0).
rev. 4.00, 03/04, page 34 of 462 2.3.3 condition code register (ccr) this 8-bit register contains internal cpu status information, including an interrupt mask bit (i), half-carry (h), negative (n), zero (z), overflow (v), and carry (c) flags. the i bit is initialized to 1 by reset exception-handling sequence, but other bits are not initialized. bit bit name initial value r/w description 7 i 1 r/w interrupt mask bit masks interrupts when set to 1. the i bit is set to 1 at the start of an exception-handling sequence. 6 u undefined r/w user bit can be written and read by software using the ldc, stc, andc, orc, and xorc instructions. 5 h undefined r/w half-carry flag when the add.b, addx.b, sub.b, subx.b, cmp.b, or neg.b instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. when the add.w, sub.w, or cmp.w instruction is executed, the h flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. 4 u undefined r/w user bit can be written and read by software using the ldc, stc, andc, orc, and xorc instructions. 3 n undefined r/w negative flag stores the value of the most significant bit of data as a sign bit. 2 z undefined r/w zero flag set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. 1 v undefined r/w overflow flag set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. 0 c undefined r/w carry flag set to 1 when a carry occurs, and cleared to 0 otherwise. used by: ? add instructions, to indicate a carry ? subtract instructions, to indicate a borrow ? shift and rotate instructions, to indicate a carry the carry flag is also used as a bit accumulator by bit manipulation instructions.
rev. 4.00, 03/04, page 35 of 462 some instructions leave flag bits unchanged. for the action of each instruction on the flag bits, refer to h8/300l series programming manual. 2.3.4 initial register values when the cpu is reset, the program counter (pc) is initialized to the value stored at address h'0000 in the vector table, and the i bit in the ccr is set to 1. the other ccr bits and the general registers are not initialized. in particular, the initial value of the stack pointer (r7) is undefined. the stack pointer should be initialized by software, by the first instruction executed after a reset. 2.4 data formats the h8/300l cpu can process 1-bit data, 4-bit (bcd) data, 8-bit (byte) data, and 16-bit (word) data. bit manipulation instructions operate on 1-bit data specified as bit n in a byte operand (n = 0, 1, 2, ..., 7). all arithmetic and logic instructions except adds and subs can operate on byte data. the mov.w, add.w, sub.w, cmp.w, adds, subs, mulxu (8 bits 8bits),anddivxu(16 bits 8 bits) instructions operate on word data. the daa and das decimal-adjust instructions treat byte data as two digits of 4-bit bcd data. 2.4.1 general register data formats figure 2.4 shows the data formats in general registers.
rev. 4.00, 03/04, page 36 of 462 data type 1-bit data 1-bit data byte data byte data word data 4-bit bcd data 4-bit bcd data rnh rnl rnh rnl rn rnh upper digit lower digit don't care don't care don't care don't care don't care upper digit lower digit don't care rnl register no. data format 76543210 7430 76543210 7430 70 70 70 0 msb lsb lsb 7 15 0 msb msb lsb llegend] rnh rnl msb lsb : upper byte of general register : lower byte of general register : most significant bit : least significant bit figure 2.4 general register data formats
rev. 4.00, 03/04, page 37 of 462 2.4.2 memory data formats figure 2.5 indicates the data formats in memory. the h8/300l cpu can access word data stored in memory (mov.w instruction), but the word data must always begin at an even address. if word data starting at an odd address is accessed, the least significant bit of the address is regarded as 0, and the word data starting at the preceding address is accessed. the same applies to instruction codes. data type address n address n even address upper 8 bits lower 8 bits odd address even address odd address even address odd address 1-bit data byte data word data byte data (ccr) on stack word data on stack address data format 76543210 70 msb lsb msb lsb ccr ccr * msb lsb msb lsb msb lsb note: * ignored on return [legend] ccr: condition code register figure 2.5 memory data formats when the stack is accessed using r7 as an address register, word access should always be performed. when the ccr is pushed on the stack, two identical copies of the ccr are pushed to make a complete word. when they are restored, the lower byte is ignored.
rev. 4.00, 03/04, page 38 of 462 2.5 instruction set the h8/300l cpu can use a total of 55 instructions, which are grouped by function in table 2.1. table 2.1 instruction set function instructions number data transfer mov, push * 1 ,pop * 1 1 arithmetic operations add, sub, addx, subx, inc, dec, adds, subs, daa, das, mulxu, divxu, cmp, neg 14 logic operations and, or, xor, not 4 shift shal, shar, shll, shlr, rotl, rotr, rotxl, rotxr 8 bit manipulation bset, bclr, bnot, btst, band, biand, bor, bior, bxor,bixor,bld,bild,bst,bist 14 branch bcc * 2 ,jmp,bsr,jsr,rts 5 system control rte, sleep, ldc, stc, andc, orc, xorc, nop 8 block data transfer eepmov 1 total: 55 notes: 1. push rn is equivalent to mov.w rn, @?sp. pop rn is equivalent to mov.w @sp+, rn. the same applies to the machine language. 2. bcc is the general name for conditional branch instructions. tables 2.3 to 2.10 summarize the instructions in each functional category. the notation used in tables2.3to2.10isdefinedbelow.
rev. 4.00, 03/04, page 39 of 462 table 2.2 operation notation symbol description rd general register (destination) rs general register (source) rn general register (ead), < ead > destination operand (eas), < eas > source operand ccr condition code register n n (negative) flag in ccr z z (zero) flag in ccr v v (overflow) flag in ccr c c (carry) flag in ccr pc program counter sp stack pointer #imm immediate data disp displacement + addition ? subtraction multiplication division logical and logical or logical xor move ? not (logical complement) :3/:8/:16 3-, 8-, or 16-bit length ( ), < > contents of operand indicated by effective address
rev. 4.00, 03/04, page 40 of 462 2.5.1 data transfer instructions table 2.3 describes the data transfer instructions. table 2.3 data transfer instructions instruction size * function mov b/w (eas) rd, rs (ead) moves data between two general registers or between a general register and memory, or moves immediate data to a general register. the rn, @rn, @(d:16, rn), @aa:16, #xx:16, @?rn, and @rn+ addressing modes are available for word data. the @aa:8 addressing mode is available for byte data only. the @?r7 and @r7+ modes require word operands. do not specify byte size for these two modes. pop w @sp+ rn pops a general register from the stack. equivalent to mov.w@sp+, rn. push w rn @?sp pushes a general register onto the stack. equivalent to mov.w rn, @? sp. note: * refers to the operand size. b: byte w: word for details on data access, see section 2.9.1, notes on data access to empty areas and section 2.9.2, access to internal i/o registers. figure 2.6 shows the instruction formats of data transfer instructions.
rev. 4.00, 03/04, page 41 of 462 15 op rm rn rm rn 87 0 15 op rm rn @rm rn 87 0 15 op rm rn @rm + rn, rn @ ? figure 2.6 instruction formats of data transfer instructions
rev. 4.00, 03/04, page 42 of 462 2.5.2 arithmetic operations instructions table 2.4 describes the arithmetic operations instructions. table 2.4 arithmetic operations instructions instruction size * function add sub b/w rd rs rd, rd + #imm rd performs addition or subtraction on data in two general registers, or addition on immediate data and data in a general register. immediate data cannot be subtracted from data in a general register. word data can be added or subtracted only when both words are in general registers. addx subx brdrsc rd, rd #imm c rd performs addition or subtraction with carry on byte data in two general registers, or addition or subtraction with carry on immediate data and data in a general register. inc dec brd1 rd increments or decrements a general register by 1. adds subs wrd1 rd, rd 2 rd adds or subtracts 1 or 2 to or from a general register. daa das b rd (decimal adjust) rd decimal-adjusts an addition or subtraction result in a general register by referring to the ccr to produce 4-bit bcd data. mulxu b rd rs rd performs 8-bit 8-bit unsigned multiplication on data in two general registers, providing a 16-bit result. divxu b rd rs rd performs 16-bit 8-bit unsigned division on data in two general registers, providing an 8-bit quotient and 8-bit remainder. cmp b/w rd?rs,rd?#imm compares data in a general register with data in another general register or with immediate data, and sets ccr bits according to the result. word data can be compared only between two general registers. neg b 0?rd rd obtains the two?s complement (arithmetic complement) of data in a general register. note: * refers to the operand size. b: byte w: word
rev. 4.00, 03/04, page 43 of 462 2.5.3 logic operations instructions table 2.5 describes the logic operations instructions. table 2.5 logic operations instructions instruction size * function and b rd rs rd, rd #imm rd performs a logical and operation on a general register and another general register or immediate data. or b rd rs rd, rd #imm rd performs a logical or operation on a general register and another general register or immediate data. xor b rd rs rd, rd #imm rd performs a logical exclusive or operation on a general register and another general register or immediate data. not b ? (rd) (rd) obtains the one's complement (logical complement) of general register contents. note: * refers to the operand size. b: byte 2.5.4 shift instructions table 2.6 describes the shift instructions. table 2.6 shift instructions instruction size * function shal shar b rd (shift) rd performs an arithmetic shift on general register contents. shll shlr b rd (shift) rd performs a logical shift on general register contents. rotl rotr b rd (rotate) rd rotates general register contents. rotxl rotxr b rd (rotate) rd rotates general register contents through the carry flag. note: * refers to the operand size. b: byte figure 2.7 shows the instruction formats of arithmetic, logic, and shift instructions.
rev. 4.00, 03/04, page 44 of 462 15 op rm rn add, sub, cmp, addx, subx (rm) 87 0 15 op rn adds, subs, inc, dec, daa, das, neg, not 87 0 15 op rm rn mulxu, divxu 87 0 15 op rn imm add, addx, subx, cmp (#xx:8) 87 0 15 op rm rn and, or, xor (rm) and, or, xor (#xx:8) 87 0 15 op imm rn 87 0 15 op rn shal, shar, shll, shlr, rotl, rotr, rotxl, rotx r 87 0 [legend] op rm, rn imm : operation field : register field : immediate data figure 2.7 instruction formats of arithmetic, logic, and shift instructions
rev. 4.00, 03/04, page 45 of 462 2.5.5 bit manipulation instructions table 2.7 describes the bit manipulation instructions. table 2.7 bit manipulation instructions (1) instruction size * function bset b 1 ( of ) sets a specified bit in a general register or memory operand to 1. the bit number is specified by 3-bit immediate data or the lower three bits of a general register. bclr b 0 ( of ) clears a specified bit in a general register or memory operand to 0. the bit number is specified by 3-bit immediate data or the lower three bits of a general register. bnot b ? ( of ) ( of ) inverts a specified bit in a general register or memory operand. the bit number is specified by 3-bit immediate data or the lower three bits of a general register. btst b ? ( of ) z tests a specified bit in a general register or memory operand and sets or clears the z flag accordingly. the bit number is specified by 3-bit immediate data or the lower three bits of a general register. band biand b b c ( of ) c ands the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. c ?(of) c ands the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. the bit number is specified by 3-bit immediate data. bor bior b b c ( of ) c ors the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. c ?(of) c ors the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. the bit number is specified by 3-bit immediate data. note: * refers to the operand size. b: byte
rev. 4.00, 03/04, page 46 of 462 table 2.7 bit manipulation instructions (2) instruction size * function bxor bixor b b c ( of ) c xors the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. c ? ( of ) c xors the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. the bit number is specified by 3-bit immediate data. bld bild b b ( of ) c transfers a specified bit in a general register or memory operand to the carry flag. ?(of) c transfers the inverse of a specified bit in a general register or memory operand to the carry flag. the bit number is specified by 3-bit immediate data. bst bist b b c ( of ) transfers the carry flag value to a specified bit in a general register or memory operand. ?c ( of ) transfers the inverse of the carry flag value to a specified bit in a general register or memory operand. the bit number is specified by 3-bit immediate data. note: * refers to the operand size. b: byte for details on the bit manipulation instructions, see section 2.9.4, bit manipulation instructions. figure 2.8 shows the instruction formats of bit manipulation instructions.
rev. 4.00, 03/04, page 47 of 462 15 op imm rn operand bit no. : register direct (rn) : immediate (#xx:3) operand bit no. : register direct (rn) : register direct (rm) operand bit no. : register indirect (@rn) : immediate (#xx:3) operand bit no. : register indirect (@rn) : register direct (rm) operand bit no. : absolute address (@aa:8) : immediate (#xx:3) operand bit no. : absolute address (@aa:8) : register direct (rm) operand bit no. : register direct (rn) : immediate (#xx:3) operand bit no. : register indirect (@rn) : immediate (#xx:3) operand bit no. : absolute address (@aa:8) : immediate (#xx:3) operand bit no. : register direct (rn) : immediate (#xx:3) operand bit no. : register indirect (@rn) : immediate (#xx:3) operand bit no. : absolute address (@aa:8) : immediate (#xx:3) 87 0 bset, bclr, bnot, btst band, bor, bxor, bld, bst imm 15 op op op op op op op op op op op op op 0000 0000 0000 0000 0000 0000 0000 0000 0000 rn rn rn rm rm 87 0 15 8 7 0 imm imm imm imm 15 abs abs abs 87 0 15 8 7 0 15 8 7 0 15 8 7 0 15 op rn rm 87 0 15 rn 87 0 [legend] op rm, rn abs imm : operation field : register field : absolute address : immediate data biand, bior, bixor, bild, bist op op op op op 0000 0000 0000 rn imm imm imm abs 15 8 7 0 15 8 7 0 15 rn 87 0 figure 2.8 instruction formats of bit manipulation instructions
rev. 4.00, 03/04, page 48 of 462 2.5.6 branch instructions table 2.8 describes the branch instructions. table 2.8 branch instructions instruction size function bcc ? branches to a specified address if a specified condition is true. the branching conditions are listed below. mnemonic description condition bra (bt) always (true) always brn (bf) never (false) never bhi high c z=0 bls low or same c z=1 bcc (bhs) carry clear (high or same) c=0 bcs (blo) carry set (low) c = 1 bne not equal z = 0 beq equal z = 1 bvc overflow clear v = 0 bvs overflow set v = 1 bpl plus n = 0 bmi minus n = 1 bge greater or equal n v=0 blt less than n v=1 bgt greater than z (n v) = 0 ble less or equal z (n v) = 1 jmp ? branches unconditionally to a specified address. bsr ? branches to a subroutine at a specified address. jsr ? branches to a subroutine at a specified address. rts ? returns from a subroutine.
rev. 4.00, 03/04, page 49 of 462 figure 2.9 shows the instruction formats of branch instructions. 15 op cc disp bcc 87 0 15 op rm 0 0 0 0 jmp (@rm) 87 0 15 op abs 87 0 15 op disp 87 0 15 op abs jmp (@aa:16) jmp (@@aa:8) bsr rts 87 0 15 op rm 0 0 0 0 jsr (@rm) 87 0 15 op abs 87 0 15 op 87 0 15 op abs jsr (@aa:16) jsr (@@aa:8) 87 0 [legend] op cc rm disp abs : operation field : condition field : register field : displacement : absolute address figure 2.9 instruction formats of branch instructions
rev. 4.00, 03/04, page 50 of 462 2.5.7 system control instructions table 2.9 describes the system control instructions. table 2.9 system control instructions instruction size * function rte ? returns from an exception-handling routine. sleep ? causes a transition from active mode to power-down mode. see section 5, power-down modes, for details. ldc b rs ccr, #imm ccr moves immediate data or general register contents to ccr. stc b ccr rd copies ccr to a specified general register. andc b ccr #imm ccr logically ands ccr with immediate data. orc b ccr #imm ccr logically ors ccr with immediate data. xorc b ccr #imm ccr logically xors ccr with immediate data. nop ? pc + 2 pc only increments the program counter. note: * refers to the operand size. b: byte figure 2.10 shows the instruction formats of system control instructions. 15 op 87 0 15 op rn 87 0 rte, sleep, nop ldc, stc (rn) 15 op imm andc, orc, xorc, ldc (#xx:8) 87 0 [legend] op rn imm : operation field : register field : immediate data figure 2.10 instruction formats of system control instructions
rev. 4.00, 03/04, page 51 of 462 2.5.8 block data transfer instructions table 2.10 describes the block data transfer instructions. table 2.10 block data transfer instructions instruction size function eepmov ? if r4l 0then repeat @r5+ @r6+ r4l?1 r4l until r4l = 0 else next; block data transfer instruction. transfers the number of data bytes specified by r4l from locations starting at the address indicated by r5 to locations starting at the address indicated by r6. after the transfer, the next instruction is executed. certain precautions are required in using the eepmov instruction. see section 2.9.3, eepmov instruction, for details. figure 2.11 shows the instruction formats of block data transfer instructions. 15 op op 87 0 [legend] op : operation field figure 2.11 instruction format of block data transfer instructions
rev. 4.00, 03/04, page 52 of 462 2.6 addressing modes and effective address 2.6.1 addressing modes the h8/300l cpu supports the eight addressing modes listed in table 2.11. each instruction uses a subset of these addressing modes. table 2.11 addressing modes no. addressing mode symbol 1 register direct rn 2 register indirect @rn 3 register indirect with displacement @(d:16,rn) 4 register indirect with post-increment register indirect with pre-decrement @rn+ @?rn 5 absolute address @aa:8/@aa:16 6 immediate #xx:8/#xx:16 7 program-counter relative @(d:8,pc) 8 memory indirect @@aa:8 register direct?rn the register field of the instruction specifies an 8- or 16-bit general register containing the operand. only the mov.w, add.w, sub.w, cmp.w, adds, subs, mulxu (8 bits 8 bits), and divxu (16 bits 8 bits) instructions have 16-bit operands. register indirect?@rn the register field of the instruction specifies a 16-bit general register containing the address of the operand in memory. register indirect with displacement?@(d:16, rn) the instruction has a second word (bytes 3 and 4) containing a displacement which is added to the contents of the specified general register (16 bits) to obtain the operand address in memory. this mode is used only in mov instructions. for the mov.w instruction, the resulting address must be even.
rev. 4.00, 03/04, page 53 of 462 register indirect with post-increment or pre-decrement?@rn+ or @-rn ? register indirect with post-increment?@rn+ the @rn+ mode is used with mov instructions that load registers from memory. the register field of the instruction specifies a 16-bit general register containing the address of the operand. after the operand is accessed, the register is incremented by 1 for mov.b or 2 for mov.w. for mov.w, the original contents of the 16-bit general register must be even. ? register indirect with pre-decrement?@?rn the @?rn mode is used with mov instructions that store register contents to memory. the register field of the instruction specifies a 16-bit general register which is decremented by 1 or 2 to obtain the address of the operand in memory. the register retains the decremented value. the size of the decrement is 1 for mov.b or 2 for mov.w. for mov.w, the original contents of the register must be even. absolute address?@aa:8/@aa:16 the instruction specifies the absolute address of the operand in memory. the absolute address may be 8 bits long (@aa:8) or 16 bits long (@aa:16). the mov.b and bit manipulation instructions can use 8-bit absolute addresses. the mov.b, mov.w, jmp, and jsr instructions can use 16-bit absolute addresses. for an 8-bit absolute address, the upper 8 bits are assumed to be 1 (h'ff). the address range is h'ff00 to h'ffff (65280 to 65535). immediate?#xx:8/#xx:16 the instruction contains an 8-bit operand (#xx:8) in its second byte, or a 16-bit operand (#xx:16) in its third and fourth bytes. only mov.w instructions can contain 16-bit immediate values. the adds and subs instructions implicitly contain the value 1 or 2 as immediate data. some bit manipulation instructions contain 3-bit immediate data in the second or fourth byte of the instruction, specifying a bit number. program-counter relative?@(d:8, pc) this mode is used in the bcc and bsr instructions. an 8-bit displacement in byte 2 of the instruction code is sign-extended to 16 bits and added to the program counter contents to generate a branch destination address. the possible branching range is ?126 to +128 bytes (?63 to +64 words) from the current address. the displacement should be an even number.
rev. 4.00, 03/04, page 54 of 462 memory indirect?@@aa:8 this mode can be used by the jmp and jsr instructions. the second byte of the instruction code specifies an 8-bit absolute address. the word located at this address contains the branch destination address. the upper 8 bits of the absolute address are assumed to be 0 (h'00), so the address range is from h'0000 to h'00ff (0 to 255). note that with the h8/300l series, the lower end of the address area is also used as a vector area. see section 3.1, exception sources and vector address, for details on the vector area. if an odd address is specified as a branch destination or as the operand address of a mov.w instruction, the least significant bit is regarded as 0, causing word access to be performed at the address preceding the specified address. see section 2.4.2, memory data formats, for further information. 2.6.2 effective address calculation table 2.12 shows how effective addresses are calculated in each of the addressing modes. arithmetic and logic instructions use register direct addressing (1). the add.b, addx, subx, cmp.b, and, or, and xor instructions can also use immediate addressing (6). data transfer instructions can use all addressing modes except program-counter relative (7) and memory indirect (8). bit manipulation instructions can use register direct (1), register indirect (2), or 8-bit absolute addressing (5) to specify the operand. register indirect (1) (bset, bclr, bnot, and btst instructions) or 3-bit immediate addressing (6) can be used independently to specify a bit position in the operand.
rev. 4.00, 03/04, page 55 of 462 table 2.12 effective address calculation 1 no. addressing mode and instruction format effective address calculation method effective address (ea) register direct rn 15 7 8430 op rm rn 2 register indirect @rn 15 6 7430 15 0 op rm 15 6 7430 op rm 15 6 7430 op rm 3 register indirect with displacement @(d:16, rn) 4 register indirect with post-increment or pre-decrement register indirect with post-increment @rn+ register indirect with pre-decrement @-rn 15 6 7430 op rm disp contents of register indicated by rm (16 bits) 15 0 15 0 15 0 contents of register indicated by rm (16 bits) disp 15 0 15 0 15 30 30 0 15 0 contents of register indicated by rm (16 bits) contents of register indicated by rm (16 bits) rm rn operand is contents of registers indicated by rm/rn 1 or 2 1 or 2 incremented or decremented by 1 if operand is byte size, and by 2 if word size
rev. 4.00, 03/04, page 56 of 462 5 no. addressing mode and instruction format effective address calculation method effective address (ea) absolute address 6 immediate 7 program-counter relative@ (d: 8, pc) @aa:8 @aa:16 #xx:8 #xx:16 15 7 80 op abs h'ff 15 7 80 op imm 15 7 80 op disp 15 0 abs op 15 0 imm op 15 0 15 0 15 7 80 pc contents sign extension disp 15 0 operand is 1- or 2-byte immediate data
rev. 4.00, 03/04, page 57 of 462 8 no. addressing mode and instruction format effective address calculation method effective address (ea) memory indirect@@aa:8 15 7 80 op abs 15 0 7 8 h'00 abs memory contents (16 bits) 15 0 [legend] rm, rn op disp imm abs : register field : operation field : displacement : immediate data : absolute address
rev. 4.00, 03/04, page 58 of 462 2.7 basic bus cycle cpu operation is synchronized by a system clock ( )orasubclock( sub ). for details on these clock signals see section 4, clock pulse generators. the period from a rising edge of or sub to the next rising edge is called one state. a bus cycle consists of two states or three states. the cycle differs depending on whether access is to on-chip memory or to on-chip peripheral modules. 2.7.1 access to on-chip memory (ram, rom) access to on-chip memory takes place in two states. the data bus width is 16 bits, allowing access in byte or word size. figure 2.12 shows the on-chip memory access cycle. t 1 state bus cycle t 2 state internal address bus internal read signal internal data bus (read access) internal write signal read data address write data internal data bus (write access) sub figure 2.12 on-chip memory access cycle
rev. 4.00, 03/04, page 59 of 462 2.7.2 on-chip peripheral modules on-chip peripheral modules are accessed in two states or three states. the data bus width is 8 bits, so access is by byte size only. this means that for accessing word data, two instructions must be used. for details on the data bus width and number of access states of each register, refer to section 14.1, register addresses (address order). two-state access to on-chip peripheral modules: figure 2.13 shows the operation timing in the case of two-state access to an on-chip peripheral module. t 1 state bus cycle t 2 state internal address bus internal read signal internal data bus (read access) internal write signal read data address write data internal data bus (write access) sub figure 2.13 on-chip peripheral module access cycle (2-state access)
rev. 4.00, 03/04, page 60 of 462 three-state access to on-chip peripheral modules: figure 2.14 shows the operation timing in the case of three-state access to an on-chip peripheral module. t 1 state bus cycle internal address bus internal read signal internal data bus (read access) internal write signal read data address internal data bus (write access) t 2 state t 3 state write data sub figure 2.14 on-chip peripheral module access cycle (3-state access)
rev. 4.00, 03/04, page 61 of 462 2.8 cpu states there are four cpu states: the reset state, program execution state, program halt state, and exception-handling state. the program execution state includes active (high-speed or medium- speed) mode and subactive mode. in the program halt state, there are a sleep (high-speed or medium-speed) mode, standby mode, watch mode, and sub-sleep mode. these states are shown in figure 2.15. figure 2.16 shows the state transitions. cpu state reset state program execution state active (high-speed) mode active (medium-speed) mode power-down modes subactive mode sleep (high-speed) mode sleep (medium-speed) mode standby mode watch mode subsleep mode program halt state a state in which the cpu operation is stopped to conserve power a transient state in which the cpu changes the processing flow due to a reset or an interrupt exception-handling state the cpu is initialized the cpu executes successive program instructions at high speed, synchronized by the system clock the cpu executes successive program instructions at reduced speed, synchronized by the system clock the cpu executes successive program instructions at reduced speed, synchronized by the subclock note: see section 5, power-down modes, for details on the modes and their transitions. figure 2.15 cpu operation states
rev. 4.00, 03/04, page 62 of 462 reset state program halt state exception-handling state program execution state reset cleared sleep instruction executed reset occurs interrupt source occurs reset occurs interrupt source occurs exception- handling complete reset occurs figure 2.16 state transitions 2.9 usage notes 2.9.1 notes on data access to empty areas the address space of this lsi includes empty areas in addition to the rom, ram, and on-chip i/o registers areas available to the user. when data is transferred from cpu to empty areas, the transferred data will be lost. this action may also cause the cpu to malfunction. when data is transferred from an empty area to cpu, the contents of the data cannot be guaranteed. 2.9.2 access to internal i/o registers internal data transfer to or from on-chip peripheral modules other than the on-chip rom and ram areas makes use of an 8-bit data width. if word access is attempted to these areas, the following results will occur. word access from cpu to i/o register area: upper byte: will be written to i/o register. lower byte: transferred data will be lost. word access from i/o register to cpu: upper byte: will be written to upper part of cpu register. lower byte: data which is written to lower part of cpu register is not guaranteed. byte size instructions should therefore be used when transferring data to or from i/o registers other than the on-chip rom and ram areas.
rev. 4.00, 03/04, page 63 of 462 2.9.3 eepmov instruction eepmov is a block-transfer instruction and transfers the byte size of data indicated by r4l, which starts from the address indicated by r5, to the address indicated by r6. set r4l and r6 so that the end address of the destination address (value of r6 + r4l) does not exceed h'ffff (the value of r6 must not change from h'ffff to h'0000 during execution). 2.9.4 bit manipulation instructions the bset, bclr, bnot, bst, and bist instructions read data from the specified address in byte units, manipulate the data of the target bit, and write data to the same address again in byte units. special care is required when using these instructions in cases where two registers are assigned to the same address or when a bit is directly manipulated for a port, because this may rewrite data of a bit other than the bit to be manipulated. bit manipulation in two registers assigned to same address: example 1: timer load register and timer counter figure 2.17 shows an example of a timer in which two timer registers are assigned to the same address. when a bit manipulation instruction accesses the timer load register and timer counter of a reloadable timer, since these two registers share the same address, the following operations takes place. 1. data is read in byte units. 2. the cpu sets or resets the bit to be manipulated with the bit manipulation instruction. 3. the written data is written again in byte units to the timer load register. the timer is counting, so the value read is not necessarily the same as the value in the timer load register. as a result, bits other than the intended bit in the timer counter may be modified and the modified value may be written to the timer load register. read write count clock timer counter timer load register reload internal data bus figure 2.17 example of timer configuration with two registers allocated to same address
rev. 4.00, 03/04, page 64 of 462 example 2: bset instruction executed designating port 3 p37 and p36 are designated as input pins, with a low-level signal input at p37 and a high-level signal at p36. the remaining pins, p35 to p31, are output pins and output low-level signals. in this example, the bset instruction is used to change pin p31 to high-level output. prior to executing bset p37 p36 p35 p34 p33 p32 p31 ? ? ? ? input/output input input output output output output output ? pin state low level high level low level low level low level low level low level ? pcr3 00111111 pdr3 10000001 bset instruction executed bset #1, @pdr3 the bset instruction is executed for port 3. after executing bset p37 p36 p35 p34 p33 p32 p31 ? ? ? ? input/output input input output output output output output ? pin state low level high level low level low level low level low level high level ? pcr3 00111111 pdr3 0 1 0000 1 1 description on operation when the bset instruction is executed, first the cpu reads port 3. since p37 and p36 are input pins, the cpu reads the pin states (low-level and high-level input). p35 to p31 are output pins, so the cpu reads the value in pdr3. in this example pdr3 has a value of h'81, but the value read by the cpu is h'41. next, the cpu sets bit 1 of the read data to 1, changing the pdr3 data to h'43. finally, the cpu writes h'43 to pdr3, completing execution of bset. as a result of the bset instruction, bit 1 in pdr3 becomes 1, and p31 outputs a high-level signal. however, bits 7 and 6 of pdr3 end up with different values. to prevent this problem, store a copy
rev. 4.00, 03/04, page 65 of 462 of the pdr3 data in a work area in memory. perform the bit manipulation on the data in the work area, then write this data to pdr3. prior to executing bset mov.b #81, r0l mov.b r0l, @ram0 mov.b r0l, @pdr3 the pdr3 value (h'81) is written to a work area in memory (ram0) as well as to pdr3. p37 p36 p35 p34 p33 p32 p31 ? ? ? ? input/output input input output output output output output ? pin state low level high level low level low level low level low level low level ? pcr3 00111111 pdr3 10000001 ram0 10000001 bset instruction executed bset #1, @ram0 the bset instruction is executed designating the pdr3 work area (ram0). after executing bset mov.b @ram0, r0l mov.b r0l, @pdr3 the work area (ram0) value is written to pdr3. p37 p36 p35 p34 p33 p32 p31 ? ? ? ? input/output input input output output output output output ? pin state low level high level low level low level low level low level high level ? pcr3 00111111 pdr3 100000 1 1 ram0 100000 1 1
rev. 4.00, 03/04, page 66 of 462 bit manipulation in register containing write-only bit example 3: bclr instruction executed designating pcr3 p37 and p36 are input pins, with a low-level signal input at p37 and a high-level signal input at p36. p35 to p31 are output pins that output low-level signals. an example of setting the p31 pin as an input pin by the bclr instruction is shown below. it is assumed that a high-level signal will be input to this input pin. prior to executing bclr p37 p36 p35 p34 p33 p32 p31 ? ? ? ? input/output input input output output output output output ? pin state low level high level low level low level low level low level low level ? pcr3 00111111 pdr3 10000001 bclr instruction executed bclr #1, @pcr3 the bclr instruction is executed for pcr3. after executing bclr p37 p36 p35 p34 p33 p32 p31 ? input/output output output output output output output input ? ? ? ? pin state low level high level low level low level low level low level high level ? ? ? ? pcr3 1 11111 0 1 pdr3 10000001 description on operation when the bclr instruction is executed, first the cpu reads pcr3. since pcr3 is a write-only register, the cpu reads a value of h'ff, even though the pcr3 value is actually h'3f. next, the cpu clears bit 1 in the read data to 0, changing the data to h'fd. finally, h'fd is written to pcr3 and bclr instruction execution ends.
rev. 4.00, 03/04, page 67 of 462 as a result of this operation, bit 1 in pcr3 becomes 0, making p31 an input port. however, bits 7 and 6 in pcr3 change to 1, so that p37 and p36 change from input pins to output pins. to prevent thisproblem,storeacopyofthepcr3datainaworkareainmemoryandmanipulatedataofthe bit in the work area, then write this data to pcr3. prior to executing bclr mov.b #3f, r0l mov.b r0l, @ram0 mov.b r0l, @pcr3 the pcr3 value (h'3f) is written to a work area in memory (ram0) as well as to pcr3. p37 p36 p35 p34 p33 p32 p31 ? input/output input input output output output output output ? ? ? ? pin state low level high level low level low level low level low level low level ? ? ? ? pcr3 00111111 pdr3 10000001 ram0 00111111 bclr instruction executed bclr #1, @ram0 the bclr instructions executed for the pcr3 work area (ram0). after executing bclr mov.b @ram0, r0l mov.b r0l, @pcr3 the work area (ram0) value is written to pcr3. p37 p36 p35 p34 p33 p32 p31 ? ? ? ? input/output input input output output output output output ? pin state low level high level low level low level low level low level high level ? pcr3 001111 0 1 pdr3 10000001 ram0 001111 0 1
rev. 4.00, 03/04, page 68 of 462 table 2.13 lists the pairs of registers that share identical addresses. table 2.14 lists the registers that contain write-only bits. table 2.13 registers with shared addresses register name abbreviation address port data register 3 * pdr3 h'ffd6 port data register 4 * pdr4 h'ffd7 port data register 5 * pdr5 h'ffd8 port data register 6 * pdr6 h'ffd9 port data register 7 * pdr7 h'ffda port data register 8 * pdr8 h'ffdb port data register a * pdra h'ffdd note: * port data registers have the same addresses as input pins. table 2.14 registers with write-only bits register name abbreviation address port control register 3 pcr3 h'ffe6 port control register 4 pcr4 h'ffe7 port control register 5 pcr5 h'ffe8 port control register 6 pcr6 h'ffe9 port control register 7 pcr7 h'ffea port control register 8 pcr8 h'ffeb port control register a pcra h'ffed timer control register f tcrf h'ffb6 pwm1 control register pwcr1 h'ffd0 pwm1 data register u pwdru1 h'ffd1 pwm1 data register l pwdrl1 h'ffd2 pwm2 control register pwcr2 h'ffcd pwm2 data register u pwdru2 h'ffce pwm2 data register l pwdrl2 h'ffcf
rev. 4.00, 03/04, page 69 of 462 section 3 exception handling exception handling may be caused by a reset or interrupts. ? reset a reset has the highest exception priority. exception handling starts as soon as the reset is cleared by the res pin. the chip is also reset when the watchdog timer overflows, and exception handling starts. exception handling is the same as exception handling by the res pin. ? interrupts external interrupts and internal interrupts are masked by the i bit in ccr, and kept masked while the i bit is set to 1. exception handling starts when the current instruction or exception handling ends, if an interrupt request has been issued. the following notes apply to the hd64f38004. ? issue depending on the circuitry status at power-on, a vector 17 (system reservation) interrupt request may be generated. if bit i in ccr is cleared to 0, this interrupt will be accepted just like any other internal interrupt. this can cause processing exceptions to occur, and program execution will eventually halt since there is no procedure for clearing the interrupt request flag in question. ? countermeasure to prevent the above issue from occurring, it is recommended that the following steps be added to programs written for the product. reset initialize stack pointer write h'9e to h'ffc3 read h'ffc3 write h'f1 to h'ffc3 write h'bf to h'fffa clear i bit in ccr user program additional steps
rev. 4.00, 03/04, page 70 of 462 the following is an example in assembler. .org h'0000 .data.w init .org h'0100 init: mov.w #h'ff80:16,sp mov.b #h'9e:8,r0l mov.b r0l,@h'ffc3:8 mov.b @h'ffc3:8,r0l mov.b #h'f1:8,r0l mov.b r0l,@h'ffc3:8 mov.b #h'bf:8,r0l mov.b r0l,@h'fffa:8 andc.b #h'7f:8,ccr ; user program the following is an example in c. void poweron_reset(void) { // ------------------------------------------------------- unsigned char dummy; *((volatile unsigned char *)0xffc3)= 0x9e; dummy = *((volatile unsigned char *)0xffc3); *((volatile unsigned char *)0xffc3)= 0xf1; *((volatile unsigned char *)0xfffa)= 0xbf; // ------------------------------------------------------- set_imask_ccr(0); // clear i bit // user program } on the mask rom version of the product, user programs may be used as is (including the additional steps described above) or without the additional steps. 3.1 exception sources and vector address table 3.1 shows the vector addresses and priority of each exception handling. when more than one interrupt is requested, handling is performed from the interrupt with the highest priority.
rev. 4.00, 03/04, page 71 of 462 table 3.1 exception sources and vector address relative module exception sources vector number vector address priority res pin watchdog timer reset 0 h'0000 to h'0001 high ? reserved for system use 1 to 3 h'0002 to h'0007 irq0/low-voltage detect interrupt * 4 h'0008 to h'0009 irq1 5 h'000a to h'000b external interrupt pin/low-voltage detect circuit (lvd) * irqaec 6 h'000c to h'000d ? reserved for system use 7, 8 h'000e to h'0011 external interrupt pin wkp0 wkp1 wkp2 wkp3 wkp4 wkp5 wkp6 wkp7 9 h'0012 to h'0013 ? reserved for system use 10 h'0014 to h'0015 timer a timer a overflow 11 h'0016 to h'0017 asynchronous event counter asynchronous event counter overflow 12 h'0018 to h'0019 ? reserved for system use 13 h'001a to h'001b timer fl compare match timer fl overflow 14 h'001c to h'001d timer f timer fh compare match timer fh overflow 15 h'001e to h'001f ? reserved for system use 16, 17 h?0020 to h?0023 sci3 transmit end transmit data empty transmit data full receive error 18 h'0024 to h'0025 a/d converter a/d conversion end 19 h'0026 to h'0027 cpu direct transition by execution of sleep instruction 20 h'0028 to h'0029 low note: * the low-voltage detection circuit and low-voltage detection interrupt are implemented on the h8/38104 group only.
rev. 4.00, 03/04, page 72 of 462 3.2 register descriptions interrupts are controlled by the following registers. ? interrupt edge select register (iegr) ? interrupt enable register 1 (ienr1) ? interrupt enable register 2 (ienr2) ? interrupt request register 1 (irr1) ? interrupt request register 2 (irr2) ? wakeup interrupt request register (iwpr) ? wakeup edge select register (wegr) 3.2.1 interrupt edge select register (iegr) iegr selects the direction of an edge that generates interrupt requests of pins and irq1 and irq0 . bit bit name initial value r/w description 7to5 ? all 1 ? reserved these bits are always read as 1. 4to2 ?? w reserved thewritevalueshouldalwaysbe0. 1 0 ieg1 ieg0 0 0 r/w r/w irq1 and irq0 edge select 0:fallingedgeof irqn pin input is detected 1: rising edge of irqn pin input is detected (n = 1 or 0)
rev. 4.00, 03/04, page 73 of 462 3.2.2 interrupt enable register 1 (ienr1) ienr1 enables timers and external pin interrupts. bit bit name initial value r/w description 7 ienta 0 r/w timer a interrupt enable enables or disables timer a overflow interrupt requests. 0: disables timer a interrupt requests 1: enables timer a interrupt requests 6 ?? w reserved thewritevalueshouldalwaysbe0. 5 ienwp 0 r/w wakeup interrupt enable enables or disables wkp7 to wkp0 interrupt requests. 0: disables wkp7 to wkp0 interrupt requests 1: enables wkp7 to wkp0 interrupt requests 4, 3 ?? w reserved thewritevalueshouldalwaysbe0. 2 ienec2 0 r/w irqaec interrupt enable enables or disables irqaec interrupt requests. 0: disables irqaec interrupt requests 1: enables irqaec interrupt requests 1 0 ien1 ien0 0 0 r/w r/w irq1 and irq0 interrupt enable enables or disables irq1 and irq0 interrupt requests. 0: disables irqn interrupt requests 1: enables irqn interrupt requests (n = 1, 0)
rev. 4.00, 03/04, page 74 of 462 3.2.3 interrupt enable register 2 (ienr2) ienr2 enables direct transition, a/d converter, and timer interrupts. bit bit name initial value r/w description 7 iendt 0 r/w direct transition interrupt enable enables or disables direct transition interrupt requests. 0: disables direct transition interrupt requests 1: enables direct transition interrupt requests 6 ienad 0 r/w a/d converter interrupt enable enables or disables a/d conversion end interrupt requests. 0: disables a/d converter interrupt requests 1: enables a/d converter interrupt requests 5, 4 ?? w reserved thewritevalueshouldalwaysbe0. 3 ientfh 0 r/w timer fh interrupt enable enables or disables timer fh compare match or overflow interrupt requests. 0: disables timer fh interrupt requests 1: enables timer fh interrupt requests 2 ientfl 0 r/w timer fl interrupt enable enables or disables timer fl compare match or overflow interrupt requests. 0: disables timer fl interrupt requests 1: enables timer fl interrupt requests 1 ?? w reserved thewritevalueshouldalwaysbe0. 0 ienec 0 r/w asynchronous event counter interrupt enable enables or disables asynchronous event counter interrupt requests. 0: disables asynchronous event counter interrupt requests 1: enables asynchronous event counter interrupt requests for details on sci3 interrupt control, refer to section 10.3.6, serial control register 3 (scr3).
rev. 4.00, 03/04, page 75 of 462 3.2.4 interrupt request register 1 (irr1) irr1 is a status flag register for timer a, irqaec, irq1, and irq0 interrupt requests. the corresponding flag is set to 1 when an interrupt request occurs. the flags are not cleared automatically when an interrupt is accepted. it is necessary to write 0 to clear each flag. bit bit name initial value r/w description 7 irrta 0 r/w * timer a interrupt request flag [setting condition] when the timer a counter value overflows from h'ff to h'00 [clearing condition] when irrta = 1, it is cleared by writing 0 6, 4, 3 ?? w reserved thewritevalueshouldalwaysbe0. 5 ? 1 ? reserved this bit is always read as 1 and cannot be modified. 2 irrec2 0 r/w * irqaec interrupt request flag [setting condition] when pin irqaec is designated for interrupt input and the designated signal edge is detected [clearing condition] when irrec2 = 1, it is cleared by writing 0 1 0 irrl1 irrl0 0 0 r/w * r/w * irq1 and irq0 interrupt request flag [setting condition] when pin irqn is designated for interrupt input and the designated signal edge is detected (n = 1, 0) [clearing condition] when irri1 and irri0 = 1, they are cleared by writing 0 note: * only 0 can be written for flag clearing.
rev. 4.00, 03/04, page 76 of 462 3.2.5 interrupt request register 2 (irr2) irr2 is a status flag register for direct transition, a/d converter, timer fh, timer fl, and asynchronous event counter interrupt requests. the corresponding flag is set to 1 when an interrupt request occurs. the flags are not cleared automatically when an interrupt is accepted. it is necessary to write 0 to clear each flag. bit bit name initial value r/w description 7 irrdt 0 r/w * direct transition interrupt request flag [setting condition] whenadirecttransitionismadebyexecutingasleep instruction while the dton bit = 1 [clearing condition] when irrdt = 1, it is cleared by writing 0 6 irrad 0 r/w * a/d converter interrupt request flag [setting condition] when a/d conversion is completed and the adsf bit is cleared to 0 [clearing condition] when irrad = 1, it is cleared by writing 0 5, 4 ?? w reserved thewritevalueshouldalwaysbe0. 3 irrtfh 0 r/w * timer fh interrupt request flag [setting condition] when tcfh and ocrfh match in 8-bit timer mode, or when tcf (tcfl, tcfh) and ocrf (ocrfl, ocrfh) match in 16-bit timer mode [clearing condition] when irrtfh = 1, it is cleared by writing 0 2 irrtfl 0 r/w * timer fl interrupt request flag [setting condition] when tcfl and ocrfl match in 8-bit timer mode [clearing condition] when irrtfl = 1, it is cleared by writing 0 1 ?? w reserved thewritevalueshouldalwaysbe0.
rev. 4.00, 03/04, page 77 of 462 bit bit name initial value r/w description 0 irrec 0 r/w * asynchronous event counter interrupt request flag [setting condition] when ech overflows in 16-bit counter mode, or ech or ecl overflows in 8-bit counter mode [clearing condition] when irrec = 1, it is cleared by writing 0 note: * only 0 can be written for flag clearing. 3.2.6 wakeup interrupt request register (iwpr) iwpr is a status flag register for wkp7 to wkp0 interrupt requests. the flags are not cleared automatically when an interrupt is accepted. it is necessary to write 0 to clear each flag. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 iwpf7 iwpf6 iwpf5 iwpf4 iwpf3 iwpf2 iwpf1 iwpf0 0 0 0 0 0 0 0 0 r/w * r/w * r/w * r/w * r/w * r/w * r/w * r/w * wakeup interrupt request flag 7 to 0 [setting condition] when pin wkpn is designated for wakeup input and the designated edge is detected (n = 7 to 0) [clearing condition] when iwpfn= 1, it is cleared by writing 0 note: * only 0 can be written for flag clearing. 3.2.7 wakeup edge select register (wegr) wegr specifies rising or falling edge sensing for pins wkpn . bit bit name initial value r/w description 7 6 5 4 3 2 1 0 wkegs7 wkegs6 wkegs5 wkegs4 wkegs3 wkegs2 wkegs1 wkegs0 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w wkpn edge select 7 to 0 selects wkpn pin input sensing. 0: wkpn pin falling edge is detected 1: wkpn pin rising edge is detected (n = 7 to 0)
rev. 4.00, 03/04, page 78 of 462 3.3 reset exception handling when the res pin goes low, all processing halts and this lsi enters the reset. the internal state of the cpu and the registers of the on-chip peripheral modules are initialized by the reset. to ensure that this lsi is reset at power-on, hold the res pin low until the clock pulse generator output stabilizes. to reset the chip during operation, hold the res pin low for at least 10 system clock cycles. when the res pin goes high after being held low for the necessary time, this lsi starts reset exception handling. the reset exception handling sequence is shown in figure 3.1. the reset exception handling sequence is as follows. however, refer to section 14.3.1, power-on reset circuit, for information on the reset sequence for the h8/38104 group, which has a built-in power-on reset function. 1. set the i bit in the condition code register (ccr) to 1. 2. the cpu generates a reset exception handling vector address (from h'0000 to h'0001), the data in that address is sent to the program counter (pc) as the start address, and program execution starts from that address. 3.4 interrupt exception handling 3.4.1 external interrupts there are external interrupts, wkp7 to wkp0, irq1, irq0, and irqaec. wkp7 to wkp0 interrupts wkp7 to wkp0 interrupts are requested by input signals to pins wkp7 to wkp0 .these interrupts have the same vector addresses, and are detected individually by either rising edge sensing or falling edge sensing, depending on the settings of bits wkegs7 to wkegs0 in wegr. when pins wkp7 to wkp0 are designated for interrupt input in pmr5 and the designated signal edge is input, the corresponding bit in iwpr is set to 1, requesting the cpu of an interrupt. these interrupts can be masked by setting bit ienwp in ienr1. irq1 and irq0 interrupts irq1 and irq0 interrupts are requested by input signals to pins irq1 and irq0 . these interrupts are given different vector addresses, and are detected individually by either rising edge sensing or falling edge sensing, depending on the settings of bits ieg1 and ieg0 in iegr. when pins irq1 and irq0 are designated for interrupt input by pmrb and pmr2 and the designated signal edge is input, the corresponding bit in irr1 is set to 1, requesting the cpu of an interrupt. these interrupts can be masked by setting bits ien1 and ien0 in ienr1.
rev. 4.00, 03/04, page 79 of 462 irqaec interrupt the irqaec interrupt is requested by an input signal to pin irqaec. this interrupt is detected by either rising edge sensing or falling edge sensing, depending on the settings of bits aiegs1 andaiegs0inaegsr. when bit ienec2 in ienr1 is designated for interrupt input and the designated signal edge is input, the corresponding bit in irr1 is set to 1, requesting the cpu of an interrupt. vector fetch each on-chip peripheral module has a flag to show the interrupt request status and the enable bit to enable or disable the interrupt. for direct transition interrupt requests generated by execution of a sleep instruction, this function is included in irr1 and irr2. when an on-chip peripheral module requests an interrupt, the corresponding interrupt request status flag is set to 1, requesting the cpu of an interrupt. when this interrupt is accepted, the i bit is set to 1 in ccr. these interrupts can be masked by writing 0 to clear the corresponding enable bit.
rev. 4.00, 03/04, page 80 of 462 3.4.3 interrupt handling sequence interrupts are controlled by an interrupt controller. interrupt operation is described as follows. 1. if an interrupt occurs while the interrupt enable bit is set to 1, an interrupt request signal is sent to the interrupt controller. 2. when multiple interrupt requests are generated, the interrupt controller requests to the cpu for the interrupt handling with the highest priority at that time according to table 3.1. other interrupt requests are held pending. 3. interrupt requests are accepted, if the i bit is cleared to 0 in ccr; if the i bit is set to 1, the interrupt request is held pending. 4. if the cpu accepts the interrupt after processing of the current instruction is completed, interrupt exception handling will begin. first, both pc and ccr are pushed onto the stack. the state of the stack at this time is shown in figure 3.2. the pc value pushed onto the stack is the address of the first instruction to be executed upon return from interrupt handling. 5. then, the i bit in ccr is set to 1, masking further interrupts. upon return from interrupt handling, the values of i bit and other bits in ccr will be restored and returned to the values prior to the start of interrupt exception handling. 6. next, the cpu generates the vector address corresponding to the accepted interrupt, and transfers the address to pc as a start address of the interrupt handling-routine. then a program starts executing from the address indicated in pc. figure 3.3 shows a typical interrupt sequence where the program area is in the on-chip rom and the stack area is in the on-chip ram. notes: 1. when disabling interrupts by clearing bits in the interrupt enable register, or when clearing bits in the interrupt request register, always do so while interrupts are masked (i = 1). 2. if the above clear operations are performed while i = 0, and as a result a conflict arises between the clear instruction and an interrupt request, exception processing for the interrupt will be executed after the clear instruction has been executed.
rev. 4.00, 03/04, page 81 of 462 pc and ccr saved to stack sp (r7) sp ? 1 sp ? 2 sp ? 3 sp ? 4 stack area sp + 4 sp + 3 sp + 2 sp + 1 sp (r7) even address prior to start of interrupt exception handling after completion of interrupt exception handling [legend] pc h : pc l : ccr: sp: upper 8 bits of program counter (pc) lower 8 bits of program counter (pc) condition code register stack pointer notes: ccr ccr * 3 pch pcl 1. 2. pc shows the address of the first instruction to be executed upon return from the interrupt handling routine. register contents must always be saved and restored by word length, starting from an even-numbered address. 3. ignored when returning from the interrupt handling routine. figure 3.2 stack status after exception handling 3.4.4 interrupt response time table 3.2 shows the number of wait states after an interrupt request flag is set until the first instruction of the interrupt handling-routine is executed. table 3.2 interrupt wait states item states total waiting time for completion of executing instruction * 1to13 15to27 saving of pc and ccr to stack 4 vector fetch 2 instruction fetch 4 internal processing 4 note: * not including eepmov instruction.
rev. 4.00, 03/04, page 82 of 462 vector fetch internal address bus internal read signal internal write signal (2) internal data bus (16 bits) interrupt request signal (9) (1) internal processing prefetch instruction of interrupt-handling routine (1) instruction prefetch address (instruction is not executed. address is saved as pc contents, becoming return address.) (2)(4) instruction code (not executed) (3) instruction prefetch address (instruction is not executed.) (5) sp ? 2 (6) sp ? 4 (7) ccr (8) vector address (9) starting address of interrupt-handling routine (contents of vector) (10) first instruction of interrupt-handling routine (3) (9) (8) (6) (5) (4) (1) (7) (10) stack access internal processing instruction prefetch interrupt level decision and wait for end of instruction interrupt is accepted figure 3.3 interrupt sequence
rev. 4.00, 03/04, page 83 of 462 3.5 usage notes 3.5.1 interrupts after reset if an interrupt is accepted after a reset and before the stack pointer (sp) is initialized, the pc and ccr will not be saved correctly, leading to a program crash. to prevent this, all interrupt requests are disabled immediately after a reset. since the first instruction of a program is always executed immediately after the reset state ends, make sure that this instruction initializes the stack pointer (example: mov.w #xx: 16, sp). 3.5.2 notes on stack area use when word data is accessed, the least significant bit of the address is regarded as 0. access to the stack always takes place in word size, so the stack pointer (sp: r7) should never indicate an odd address. use push rn (mov.w rn, @?sp) or pop rn (mov.w @sp+, rn) to save or restore register values. 3.5.3 notes on rewriting port mode registers when a port mode register is rewritten to switch the functions of external interrupt pins, irqaec, irq1 , irq0 ,and wkp7 to wkp0 , the interrupt request flag may be set to 1. when switching a pin function, mask the interrupt before setting the bit in the port mode register. after accessing the port mode register, execute at least one instruction (e.g., nop), then clear the interrupt request flag from 1 to 0. table 3.3 lists the interrupt request flags which are set to 1 and the conditions. table 3.3 conditions under which interrupt request flag is set to 1 interrupt request flags set to 1 conditions irrec2 when the edge designated by aiegs1 and aiegs0 in aegsr is input while ienec2 in ienri is set to 1. irri1 when irq1 bit in pmrb is changed from 0 to 1 while pin irq1 is low and ieg1 bit in iegr = 0. when irq1 bit in pmrb is changed from 1 to 0 while pin irq1 is low and ieg1 bit in iegr = 1. irr1 irri0 when irq0 bit in pmr2 is changed from 0 to 1 while pin irq0 is low and ieg0 bit in iegr = 0. when irq0 bit in pmr2 is changed from 1 to 0 while pin irq0 is low and ieg0 bit in iegr = 1.
rev. 4.00, 03/04, page 84 of 462 interrupt request flags set to 1 conditions iwpf7 when pmr5 bit wkp7 is changed from 0 to 1 while pin wkp7 is low and wegr bit wkegs7 = 0. when pmr5 bit wkp7 is changed from 1 to 0 while pin wkp7 is low and wegr bit wkegs7 = 1. iwpf6 when pmr5 bit wkp6 is changed from 0 to 1 while pin wkp6 is low and wegr bit wkegs6 = 0. when pmr5 bit wkp6 is changed from 1 to 0 while pin wkp6 is low and wegr bit wkegs6 = 1. iwpf5 when pmr5 bit wkp5 is changed from 0 to 1 while pin wkp5 is low and wegr bit wkegs5 = 0. when pmr5 bit wkp5 is changed from 1 to 0 while pin wkp5 is low and wegr bit wkegs5 = 1. iwpf4 when pmr5 bit wkp4 is changed from 0 to 1 while pin wkp4 is low and wegr bit wkegs4 = 0. when pmr5 bit wkp4 is changed from 1 to 0 while pin wkp4 is low and wegr bit wkegs4 = 1. iwpf3 when pmr5 bit wkp3 is changed from 0 to 1 while pin wkp3 is low and wegr bit wkegs3 = 0. when pmr5 bit wkp3 is changed from 1 to 0 while pin wkp3 is low and wegr bit wkegs3 = 1. iwpf2 when pmr5 bit wkp2 is changed from 0 to 1 while pin wkp2 is low and wegr bit wkegs2 = 0. when pmr5 bit wkp2 is changed from 1 to 0 while pin wkp2 is low and wegr bit wkegs2 = 1. iwpf1 when pmr5 bit wkp1 is changed from 0 to 1 while pin wkp1 is low and wegr bit wkegs1 = 0. when pmr5 bit wkp1 is changed from 1 to 0 while pin wkp1 is low and wegr bit wkegs1 = 1. iwpr iwpf0 when pmr5 bit wkp0 is changed from 0 to 1 while pin wkp0 is low and wegr bit wkegs0 = 0. when pmr5 bit wkp0 is changed from 1 to 0 while pin wkp0 is low and wegr bit wkegs0 = 1.
rev. 4.00, 03/04, page 85 of 462 3.5.4 interrupt request flag clearing method use the following recommended method for flag clearing in the interrupt request registers (irr1, irr2, and iwpr). recommended method: perform flag clearing with only one instruction. either a bit manipulation instruction or a data transfer instruction in bytes can be used. two examples of coding for clearing irri1 (bit 1 in irr1) are shown below: ? bcr #1,@irr1:8 ? mov.b r1l,@irr1:8 (set b 11111101 to r1l in advance) malfunction example: when flag clearing is performed with several instructions, a flag, other than the intended one, which was set while executing one of those instructions may be accidentally cleared, and thus cause incorrect operations to occur. an example of coding for clearing irri1 (bit 1 in irr1), in which irri0 is also cleared and the interrupt becomes invalid is shown below. mov.b @irr1:8,r1l at this point, irri0 is 0. and.b #b 11111101,r1l irri0 becomes 1 here. mov.b r1l,@irr1:8 irri0 is cleared to 0. in the above example, an irq0 interrupt occurs while the and.b instruction is executed. since not only the original target irri1, but also irri0 is cleared to 0, the irq0 interrupt becomes invalid. figure 3.4 shows a port mode register setting and interrupt request flag clearing procedure. ccr i bit 1 set port mode register bit execute nop instruction interrupts masked. (another possibility is to disable the relevant interrupt in interrupt enable register 1.) after setting the port mode register bit, first execute at least one instruction (e.g., nop), then clear the interrupt request flag to 0 interrupt mask cleared clear interrupt request flag to 0 ccr i bit 0
rev. 4.00, 03/04, page 86 of 462
cpg0201a_000020020900 rev. 4.00, 03/04, page 87 of 462 section 4 clock pulse generators 4.1 features clock oscillator circuitry (cpg: clock pulse generator) is provided on-chip, including both a system clock pulse generator and a subclock pulse generator. in the h8/38104 group, the system clock pulse generator includes an on-chip oscillator. the system clock pulse generator consists of a system clock oscillator and system clock dividers. the subclock pulse generator consists of a subclock oscillator and a subclock divider. figure 4.1 shows a block diagram of the clock pulse generators of the h8/3802 and h8/38004 group. figure 4.2 shows a block diagram of the clock pulse generators of the h8/38104 group. system clock oscillator subclock oscillator subclock divider (1/2, 1/4, 1/8) system clock divider (1/2) system clock divider prescaler s (13 bits) prescaler w (5 bits) osc1 osc2 x1 x2 system clock pulse generator subclock pulse generator osc (f osc) w (f w ) w /2 w /4 sub w /2 to to w /2 w /4 w /8 w /128 /8192 w /8 osc /2 osc /16 osc /32 osc /64 osc /128 figure 4.1 block diagram of clock pulse generators (h8/3802, h8/38004 group)
rev. 4.00, 03/04, page 88 of 462 system clock oscillator subclock oscillator subclock divider (1/2, 1/4, 1/8) system clock divider (1/2) system clock divider prescaler s (13 bits) prescaler w (5 bits) osc1 latch on-chip oscillator internal reset signal c dq irqaec osc2 x1 x2 system clock pulse generator subclock pulse generator osc (f osc ) r osc w (f w ) w /2 w /4 sub w /2 to /8192 w /2 w /4 w /8 to w /128 w /8 osc /2 osc /16 osc /32 osc /64 osc /128 figure 4.2 block diagram of clock pulse generators (h8/38104 group) the basic clock signals that drive the cpu and on-chip peripheral modules are and sub .the system clock is divided by prescaler s to become a clock signal from /8192 to /2, and the subclock is divided by prescaler w to become a clock signal from w/128 to w/8. both the system clock and subclock signals are provided to the on-chip peripheral modules.
rev. 4.00, 03/04, page 89 of 462 4.2 register description oscillator control register (osccr) (h8/38104 group only) osccr contains a flag indicating the selection status of the system clock oscillator and on-chip oscillator, indicates the input level of the irqaec pin during resets, and controls whether the subclock oscillator operates or not. bit bit name initial value r/w description 7 substp 0 r/w subclock oscillator stop control 0: subclock oscillator operates 1: subclock oscillator stopped note: bit 7 can be set to 1 only in the active mode (high- speed/medium-speed). setting bit 7 to 1 in the subactive mode will cause the lsi to stop operating. 6 ? 0rreserved this bit is always read as 0 5to3 ? all 0 r/w reserved these bits are read/write enabled reserved bits. 2 irqaecf ? r irqaec flag this bit indicates the irqaec pin input level set during resets. 0: irqaec pin set to gnd during resets 1: irqaec pin set to v cc during resets 1oscf ? roscflag this bit indicates the oscillator operating with the system clock pulse generator. 0: system clock oscillator operating (on-chip oscillator stopped) 1: ring oscillator operating (system clock oscillator stopped) 0 ? 0r/wreserved neverwrite1tothisbit,asitcancausethelsito malfunction.
rev. 4.00, 03/04, page 90 of 462 4.3 system clock generator clock pulses can be supplied to the system clock divider either by connecting a crystal or ceramic resonator, or by providing external clock input. figure 4.3 shows a block diagram of the system clock generator. as shown in figure 4.2, the h8/38104 group supports selection between a system clock oscillator and an on-chip oscillator. see section 4.3.4, on-chip oscillator selection method, for information on selecting the on-chip oscillator. lpm power-down mode (standby mode, subactive mode, subsleep mode, watch mode) osc2 osc1 note: lpm: figure 4.3 block diagram of system clock generator 4.3.1 connecting crystal resonator figure 4.4(1) shows a typical method of connecting a crystal oscillator to the h8/3802 group, and figure 4.4(2) shows a typical method of connecting a crystal oscillator to the h8/38004 and h8/38104 group. figure 4.5 shows the equivalent circuit of a crystal resonator. a resonator having the characteristics given in table 4.1 should be used. c 1 c rf 2 osc1 osc2 frequency manufacturer c1, c2 recommendation value 4.19 mhz nihon dempa kogyo co., ltd. note: consult with the crystal resonator manufacturer to determine the circuit constants. 12 pf 20% c = c = 12 pf 20% rf = 1 m ? 20% 12 figure 4.4(1) typical connection to crystal resonator (h8/3802 group)
rev. 4.00, 03/04, page 91 of 462 c 1 c rf 2 osc1 osc2 frequency manufacturer c1, c2 recommendation value prodoct name 4.0 mhz nihon dempa kogyo co., ltd. nr-18 note: consult with the crystal resonator manufacturer to determine the circuit constants. 12 pf 20% rf = 1 m ? 20% figure 4.4(2) typical connection to crystal resonator (h8/38004, h8/38104 group) c s c 0 r s osc1 osc2 l s figure 4.5 equivalent circuit of crystal resonator table 4.1 crystal resonator parameters frequency (mhz) 4.10 4.193 r s (max) 100 ? c 0 (max) 16 pf 4.3.2 connecting ceramic resonator figure 4.6(1) shows a typical method of connecting a ceramic oscillator to the h8/3802 group, and figure 4.6(2) shows a typical method of connecting a crystal oscillator to the h8/38004 and h8/38104 group. osc1 osc2 c 1 c 2 c = c = 30 pf 10% rf = 1 m ? 20% 12 rf frequency manufacturer c1, c2 recommendation value 4.0 mhz murata manufacturing co., ltd. note: consult with the ceramic resonator manufacturer to determine the circuit constants. 30 pf 10% figure 4.6(1) typical connection to ceramic resonator (h8/3802 group)
rev. 4.00, 03/04, page 92 of 462 osc1 osc2 c 1 c 2 rf murata manufacturing co., ltd. frequency ceramic resonator manufacturer c1, c2 recommendation value prodoct name 2.0 mhz 10.0 mhz 16.0 mhz * cstcc2m00g53-b0 cstcc2m00g56-b0 cstls10m0g53-b0 cstls10m0g56-b0 cstls16m0x53-b0 note: consult with the crystal resonator manufacturer to determine the circuit constants. * this does not apply to the h8/38004 group. 15 pf 20% 47 pf 20% 15 pf 20% 47 pf 20% 15 pf 20% rf = 1 m ? 20% figure 4.6(2) typical connection to ceramic resonator (h8/38004, h8/38104 group) 4.3.3 external clock input method connect an external clock signal to pin osc1, and leave pin osc2 open. figure 4.6 shows a typical connection. the duty cycle of the external clock signal must be 45 to 55%. osc1 external clock input osc2 open figure 4.7 example of external clock input 4.3.4 on-chip oscillator selection method (h8/38104 group only) the on-chip oscillator is selected by setting the irqaec pin input level during resets. the irqaec pin input level set during resets must be fixed at v cc or gnd, based on the oscillator to be selected. it is not necessary to connect an oscillator to pins osc1 and osc2 if the on-chip oscillator is selected. in this case, pin osc1 should be fixed at v cc or gnd. note: the system clock oscillator must be selected in order to program or erase flash memory as part of operations such as on-board programming. also, when using the on-chip emulator, an oscillator should be connected, or an external clock input, even if the on-chip oscillator is selected.
rev. 4.00, 03/04, page 93 of 462 table 4.2 system clock oscillator and on-chip oscillator selection methods irqaec pin input level (during resets) 01 system clock oscillator enabled disabled on-chip oscillator disabled enabled 4.4 subclock generator figure 4.8 shows a block diagram of the subclock generator. note that on the h8/38104 group the subclock oscillator can be disabled by programs by setting the substp bit in the osccr register. the register setting to disable the subclock oscillator should be made in the active mode. when restoring operation of the subclock oscillator after it has been disabled using the osccr register, it is necessary to wait for the oscillation stabilization time (typ = 8s) to elapse before using the subclock. note : resistance is a reference value. 2 10 m 1 x x figure 4.8 block diagram of subclock generator 4.4.1 connecting 32.768-khz/38.4-khz crystal resonator clock pulses can be supplied to the subclock divider by connecting a 32.768-khz or 38.4-khz crystal resonator, as shown in figure 4.9. figure 4.10 shows the equivalent circuit of the 32.768- khz or 38.4-khz crystal resonator. note that only operation at 32.768 khz is guaranteed on the h8/38104 group. x1 x2 c 1 c 2 c = c = 15 pf (typ.) 12 frequency manufacturer product name 38.4 khz seiko instruments inc. note: consult with the crystal resonator manufacturer to determine the circuit constants. vtc-200 32.768 khz nihon dempa kogyo co., ltd. mx73p figure 4.9 typical connection to 32.768-khz/38.4-khz crystal resonator
rev. 4.00, 03/04, page 94 of 462 x1 x2 l s c s c o c o = 1.5 pf (typ.) r s = 14 k ? (typ.) f w = 32.768 khz/38.4 khz r s note: constants are reference values. figure 4.10 equivalent circuit of 32.768-khz/38.4-khz crystal resonator 4.4.2 pin connection when not using subclock when the subclock is not used, connect pin x1 to gnd and leave pin x2 open, as shown in figure 4.11. x1 gnd x2 open figure 4.11 pin connection when not using subclock 4.4.3 external clock input connect the external clock to pin x1 and leave pin x2 open, as shown in figure 4.12. note that input of an external clock is not supported on the h8/38104 group. x1 x2 external clock input open figure 4.12 pin connection when inputting external clock frequency subclock ( w ) duty 45 % to 55 %
rev. 4.00, 03/04, page 95 of 462 4.5 prescalers 4.5.1 prescaler s prescaler s is a 13-bit counter using the system clock ( ) as its input clock. it is incremented once per clock period. prescaler s is initialized to h'0000 by a reset, and starts counting on exit from the reset state. in standby mode, watch mode, subactive mode, and subsleep mode, the system clock pulse generator stops. prescaler s also stops and is initialized to h'0000. the cpu cannot read or write prescaler s. the output from prescaler s is shared by the on-chip peripheral modules. the division ratio can be set separately for each on-chip peripheral function. in active (medium- speed) mode and sleep mode, the clock input to prescaler s is determined by the division ratio designated by the ma1 and ma0 bits in syscr2. 4.5.2 prescaler w prescaler w is a 5-bit counter using a 32.768 khz or 38.4 khz signal divided by 4 ( w /4) as its input clock. the divided output is used for clock time base operation of timer a. prescaler w is initialized to h'00 by a reset, and starts counting on exit from the reset state. even in standby mode, watch mode, subactive mode, or subsleep mode, prescaler w continues functioning. prescaler w can be reset by setting 1s in bits tma3 and tma2 in tma. 4.6 usage notes 4.6.1 note on resonators resonator characteristics are closely related to board design and should be carefully evaluated by the user, referring to the examples shown in this section. resonator circuit constants will differ depending on the resonator element, stray capacitance in its interconnecting circuit, and other factors. suitable constants should be determined in consultation with the resonator manufacturer. design the circuit so that the resonator never receives voltages exceeding its maximum rating.
rev. 4.00, 03/04, page 96 of 462 (vss) pb3 x1 x2 vss osc2 osc1 test figure 4.13 example of crystal and ceramic resonator arrangement figure 4.14 (1) shows an example of the measurement circuit for the negative resistor which is recommended by the resonator manufacturer. note that if the negative resistor in this circuit does not reach the level which is recommended by the resonator manufacturer, the main oscillator may be hard to start oscillation. if the negative resistor does not reach the level which is recommended by the resonator manufacturer and oscillation is not started, changes as shown in figure 4.14 (2) to (4) should be made. the proposed change and capacitor size to be applied should be determined according to the evaluation result of the negative resistor and frequency deviation, etc.
rev. 4.00, 03/04, page 97 of 462 change os c1 negative resistor -r added (1) negative resistor measurement circuit (2) proposed change in oscillator circuit 1 (3) proposed change in oscillator circuit 2 (4) proposed change in oscillator circuit 3 change change os c2 c 1 c 2 rf osc 1 osc 2 c 1 c 2 rf osc 1 osc 2 c 1 c 2 rf osc 1 osc 2 c 1 c 2 rf c 3 figure 4.14 negative resistor measurement and proposed changes in circuit 4.6.2 notes on board design when using a crystal resonator (ceramic resonator), place the resonator and its load capacitors as close as possible to the osc1 and osc2 pins. other signal lines should be routed away from the resonator circuit to prevent induction from interfering with correct oscillation (see figure 4.15). osc1 osc2 c 1 c 2 signal a signal b avoid figure 4.15 example of incorrect board design
rev. 4.00, 03/04, page 98 of 462 4.6.3 definition of oscillation stabilization standby time figure 4.16 shows the oscillation waveform (osc2), system clock ( ), and microcomputer operating mode when a transition is made from standby mode, watch mode, or subactive mode, to active (high-speed/medium-speed) mode, with a resonator connected to the system clock oscillator. as shown in figure 4.16, as the system clock oscillator is halted in standby mode, watch mode, and subactive mode, when a transition is made to active (high-speed/medium-speed) mode, the sum of the following two times (oscillation stabilization time and standby time) is required. 1. oscillation stabilization time (t rc ) the time from the point at which the oscillation waveform of the system clock oscillator starts to change when an interrupt is generated, until the amplitude of the oscillation waveform increases and the oscillation frequency stabilizes. 2. standby time the time required for the cpu and peripheral functions to begin operating after the oscillation waveform frequency and system clock have stabilized. the standby time setting is selected with standby timer select bits 2 to 0 (sts2 to sts0) (bits 6 to 4 in the system control register 1 (syscr1)). oscillation waveform (osc2) system clock ( figure 4.16 oscillation stabilization standby time
rev. 4.00, 03/04, page 99 of 462 when standby mode, watch mode, or subactive mode is cleared by an interrupt or reset, and a transition is made to active (high-speed/medium-speed) mode, the oscillation waveform begins to change at the point at which the interrupt is accepted. therefore, when a resonator is connected in standby mode, watch mode, or subactive mode, since the system clock oscillator is halted, the time from the point at which this oscillation waveform starts to change until the amplitude of the oscillation waveform increases and the oscillation frequency stabilizes?that is, the oscillation stabilization time?is required. the oscillation stabilization time in the case of these state transitions is the same as the oscillation stabilization time at power-on (the time from the point at which the power supply voltage reaches the prescribed level until the oscillation stabilizes), specified by "oscillation stabilization time t rc " in the ac characteristics. meanwhile, once the system clock has halted, a standby time of at least 8 states is necessary in order for the cpu and peripheral functions to operate normally. thus, the time required from interrupt generation until operation of the cpu and peripheral functions is the sum of the above described oscillation stabilization time and standby time. this total time is called the oscillation stabilization standby time, and is expressed by equation (1) below. oscillation stabilization standby time = oscillation stabilization time + standby time =t rc + (8 to 16,384 states) ................. (1) therefore, when a transition is made from standby mode, watch mode, or subactive mode, to active (high-speed/medium-speed) mode, with a resonator connected to the system clock oscillator, careful evaluation must be carried out on the installation circuit before deciding on the oscillation stabilization standby time. in particular, since the oscillation settling time is affected by installation circuit constants, stray capacitance, and so forth, suitable constants should be determined in consultation with the resonator manufacturer. 4.6.4 notes on use of crystal resonator (excluding ceramic resonator) when a microcomputer operates, the internal power supply potential fluctuates slightly in synchronization with the system clock. depending on the individual crystal resonator characteristics, the oscillation waveform amplitude may not be sufficiently large immediately after the oscillation stabilization standby time, making the oscillation waveform susceptible to influence by fluctuations in the power supply potential. in this state, the oscillation waveform may be disrupted, leading to an unstable system clock and erroneous operation of the microcomputer. if erroneous operation occurs, change the setting of standby timer select bits 2 to 0 (sts2 to sts0) (bits 6 to 4 in system control register 1 (syscr1)) to give a longer standby time.
rev. 4.00, 03/04, page 100 of 462 for example, if erroneous operation occurs with a standby time setting of 16 states, check the operation with a standby time setting of 1,024* states or more. if the same kind of erroneous operation occurs after a reset as after a state transition, hold the res pin low for a longer period. note: * this figure applies to the h8/3802 and h8/38004 groups. the number of states on the h8/38104 group is 8,192 or more. 4.6.5 notes on h8/38104 group when using the on-chip emulator, system clock precision is necessary for programming or erasing the flash memory. however, the on-chip oscillator frequency can vary due to changes in conditions such as voltage or temperature. consequently, when using the on-chip emulator, pins osc1 and osc2 should be connected to an oscillator, or an external clock should be supplied, if the on-chip oscillator is selected. in this case, the lsi uses the on-chip oscillator when user programs are being executed and the system clock oscillator when programming or erasing flash memory. the process is controlled by the on-chip emulator.
rev. 4.00, 03/04, page 101 of 462 section 5 power-down modes this lsi has eight modes of operation after a reset. these include a normal active (high-speed) mode and seven power-down modes, in which power consumption is significantly reduced. the module standby function reduces power consumption by selectively halting on-chip module func- tions. ? active (medium-speed) mode the cpu and all on-chip peripheral modules are operable on the system clock. the system clock frequency can be selected from osc/16, osc/32, osc/64, and osc/128. ? subactive mode the cpu and all on-chip peripheral modules are operable on the subclock. the subclock fre- quency can be selected from w/2, w/4, and w/8. ? sleep (high-speed) mode the cpu halts. on-chip peripheral modules are operable on the system clock. ? sleep (medium-speed) mode the cpu halts. on-chip peripheral modules are operable on the system clock. the system clock frequency can be selected from osc/16, osc/32, osc/64, and osc/128. ? subsleep mode the cpu halts. the timer a, timer f, sci3, aec, and lcd controller/driver are operable on the subclock. the subclock frequency can be selected from w/2, w/4, and w/8. ? watch mode the cpu halts. timer a's timekeeping function, timer f, aec, and lcd controller/driver are operable on the subclock. ? standby mode the cpu and all on-chip peripheral modules halt. ? module standby function independent of the above modes, power consumption can be reduced by halting on-chip pe- ripheral modules that are not used in module units. note: in this manual, active (high-speed) mode and active (medium-speed) mode are collectively called active mode.
rev. 4.00, 03/04, page 102 of 462 5.1 register descriptions the registers related to power-down modes are as follows. ? system control register 1 (syscr1) ? system control register 2 (syscr2) ? clockhaltregisters1and2(ckstpr1andckstpr2) 5.1.1 system control register 1 (syscr1) syscr1 controls the power-down modes, as well as syscr2. bit bit name initial value r/w description 7 ssby 0 r/w software standby selects the mode to transit after the execution of the sleep instruction. 0: a transition is made to sleep mode or subsleep mode. 1: a transition is made to standby mode or watch mode. for details, see table 5.2. 6 5 4 sts2 sts1 sts0 0 0 0 r/w r/w r/w standby timer select 2 to 0 designate the time the cpu and peripheral modules wait for stable clock operation after exiting from standby mode, subactive mode, subsleep mode, or watch mode to active mode or sleep mode due to an interrupt. the designation should be made according to the operating frequency so that the waiting time is at least equal to the oscillation stabilization time. the relationship between the specified value and the number of wait states is shown in tables 5.1(1) and 5.1(2). when an external clock is to be used, the minimum value (sts2 = 1, sts1 = 0, sts0 = 1) is recommended. 8,192 states (sts2 = sts1 = sts0 = 0) is recommended if the on-chip oscillator is used on the h8/38104 group. if the setting other than the recommended value is made, op- eration may start before the end of the waiting time. 3 lson 0 r/w selects the system clock ( )orsubclock( sub )asthe cpu operating clock when watch mode is cleared. 0: the cpu operates on the system clock ( ) 1: the cpu operates on the subclock ( sub ) 2 ? 1 ? reserved this bit is always read as 1 and cannot be modified.
rev. 4.00, 03/04, page 103 of 462 bit bit name initial value r/w description 1 0 ma1 ma0 1 1 r/w r/w active mode clock select 1 and 0 select osc /16, osc /32, osc /64, or osc /128 as the op- erating clock in active (medium-speed) mode and sleep (medium-speed) mode. the ma1 and ma0 bits should be written to in active (high-speed) mode or subactive mode. 00: osc /16 01: osc /32 10: osc /64 11: osc /128 table 5.1(1) operating frequency and waiting time (h8/3802 group, h8/38004 group) bit operating frequency sts2 sts1 sts0 waiting time 5 mhz 2 mhz 0 0 0 8,192 states 1.638 4.1 1 16,384 states 3.277 8.2 1 0 1,024 states 0.205 0.512 1 2,048 states 0.410 1.024 1 0 0 4,096 states 0.819 2.048 1 2 states (external clock input) 0.0004 0.001 1 0 8 states 0.002 0.004 1 16 states 0.003 0.008 table 5.1(2) operating frequency and waiting time (h8/38104 group) bit operating frequency sts2 sts1 sts0 waiting time 5 mhz 2 mhz 0 0 0 8,192 states 1.638 4.1 1 16,384 states 3.277 8.2 1 0 32,768 states 6.554 16.4 1 65,536 states 13.108 32.8 1 0 0 131,072 states 26.216 65.5 1 2 states (external clock input) 0.0004 0.001 1 0 8 states 0.002 0.004 1 16 states 0.003 0.008 note: the time unit is ms. if external clock input is used, sts2 to sts0 should be set to the external clock input mode
rev. 4.00, 03/04, page 104 of 462 before the mode transition is executed. in addition, sts2 to sts0 should not be set to the external clock input mode if external clock input is not used. when the on-chip clock oscil- lator is used on the h8/38104 group, a setting of 8,192 states (sts2 = sts1 = sts0 = 0) is recommended. 5.1.2 system control register 2 (syscr2) syscr2 controls the power-down modes, as well as syscr1. bit bit name initial value r/w description 7to5 ? all 1 ? reserved these bits are always read as 1 and cannot be modi- fied. 4 nesel 1 r/w noise elimination sampling frequency select selects the frequency at which the watch clock signal ( w ) generated by the subclock pulse generator is sam- pled, in relation to the oscillator clock ( osc ) generated by the system clock pulse generator. when osc =2to 16 mhz, clear this bit to 0. 0: sampling rate is osc /16. 1: sampling rate is osc /4. 3dton0r/wdirecttransferonflag selects the mode to which the transition is made after the sleep instruction is executed with bits ssby and lson in syscr1, bit mson in syscr2, and bit tma3 in tma. for details, see table 5.2. 2 mson 0 r/w medium speed on flag after standby, watch, or sleep mode is cleared, this bit selects active (high-speed) or active (medium-speed) mode. 0: operation in active (high-speed) mode 1: operation in active (medium-speed) mode 1 0 sa1 sa0 0 0 r/w r/w subactive mode clock select 1 and 0 select the operating clock frequency in subactive and subsleep modes. the operating clock frequency changes to the set frequency after the sleep instruc- tion is executed. 00: w /8 01: w /4 1x: w /2 [legend] x: don't care.
rev. 4.00, 03/04, page 105 of 462 5.1.3 clock halt registers 1 and 2 (ckstpr1 and ckstpr2) ckstpr1 and ckstpr2 allow the on-chip peripheral modules to enter a standby state in module units. ? ckstpr1 bit bit name initial value r/w description 7, 6 ? all 1 ? reserved 5 s32ckstp 1 r/w sci module standby sci3 enters standby mode when this bit is cleared to 0. * 2 4 adckstp 1 r/w a/d converter module standby a/d converter enters standby mode when this bit is cleared to 0. 3 ? 1 ? reserved 2 tfckstp 1 r/w timer f module standby timer f enters standby mode when this bit is cleared to 0. 1 ? 1 ? reserved 0 tackstp 1 r/w timer a module standby * 3 timer a enters standby mode when this bit is cleared to 0. ? ckstpr2 bit bit name initial value r/w description 7 lvdckstp 1 r/w lvd module standby the lvd module enters standby status when this bit is cleared to 0. note: on products other than the h8/38104 group, this bit is reserved like bits 6 and 5. 6, 5 ? all 1 ? reserved 4 pw2ckstp 1 r/w * 1 pwm2 module standby pwm2 enters standby mode when this bit is cleared to 0. 3 aeckstp 1 r/w asynchronous event counter module standby asynchronous event counter enters standby mode when this bit is cleared to 0
rev. 4.00, 03/04, page 106 of 462 bit bit name initial value r/w description 2 wdckstp 1 r/w * 4 watchdog timer module standby watchdog timer enters standby mode when this bit is cleared to 0 1 pw1ckstp 1 r/w pwm1 module standby pwm1 enters standby mode when this bit is cleared to 0 0 ldckstp 1 r/w lcd module standby lcd controller/driver enters standby mode when this bit is cleared to 0 notes: 1. this bit cannot be read or written in the h8/3802 group. 2. when the sci module standby is set, all registers in the sci3 enter the reset state. 3. when the timer a module standby is set, the tma3 bit in tma cannot be rewritten. when the tma3 bit is rewritten, the tackstp bit in ckstpr1 should be set to 1 in advance. 4. this bit cannot be read or written in the h8/3802 group. this bit is valid when the wdon bit in tcsrw is 0. if this bit is cleared to 0 while the wdon bit is set to 1 (while the watchdog timer is operating), this bit is cleared to 0. however, the watchdog timer does not enter module standby mode and continues operating. when the watchdog timer stops operating and the wdon bit is cleared to 0 by software, this bit is valid and the watchdog timer enters module standby mode. 5.2 mode transitions and states of lsi figure 5.1 shows the possible transitions among these operating modes. a transition is made from the program execution state to the program halt state of the program by executing a sleep in- struction. interrupts allow for returning from the program halt state to the program execution state of the program. a direct transition between active mode and subactive mode, which are both pro- gram execution states, can be made without halting the program. the operating frequency can also be changed in the same modes by making a transition directly from active mode to active mode, and from subactive mode to subactive mode. res input enables transitions from a mode to the reset state. table 5.2 shows the transition conditions of each mode after the sleep instruction is executed and a mode to return by an interrupt. table 5.3 shows the internal states of the lsi in each mode.
rev. 4.00, 03/04, page 107 of 462 reset state standby mode watch mode active (high-speed mode) sleep (high-speed) mode active (medium-speed) mode sleep (medium-speed) mode subactive mode subsleep mode power-down modes : transition is made after exception handling is executed. program halt state program execution state program halt state note: a transition between different modes cannot be made to occur simply because an interrupt request is generated. make sure that interrupt handling is performed after the interrupt is accepted. sleep instruction sleep instruction sleep instruction sleep instruction sleep instruction sleep instruction sleep instruction sleep instruction slee p instruction slee p instruction b a d d 4 3 3 1 1 2 4 f g a b e e e 1 j i i c h lson mson ssby tma3 dton a 0 0 0 * 0 b 0 1 0 * 0 c 1 * 0 1 0 d 0 * 1 0 0 e * * 1 1 0 f 0 0 0 * 1 g 0 1 0 * 1 h 0 1 1 1 1 i 1 * 1 1 1 j 0 0 1 1 1 interrupt sources timer a, timer f interrupt, irq0 interrupt, wkp7 to wkp0 interrupts timer a, timer f, sci3 interrupt, irq1 and irq0 interrupts, irqaec, wkp7 o wkp0 interrupts, aec all interrupts irq1 or irq0 interrupt, wkp7 to wkp0 interrupts * don't care mode transition conditions (1) mode transition conditions (2) sleep instruction sleep instruction sleep instruction sleep instruction sleep instruction sleep instruction 1 2 3 4 figure 5.1 mode transition diagram
rev. 4.00, 03/04, page 108 of 462 table 5.2 transition mode after sleep instruction execution and interrupt handling lson mson ssby tma3 dton transition mode after sleep instruction execution transition mode due to interrupt 0 0 0 x 0 sleep (high-speed) mode active (high-speed) mode 0 1 0 x 0 sleep (medium-speed) mode active (medium-speed) mode 1x010subsleepmode s ubactive mode 0x100st andby mode active mode xx110watchmode activem ode, subactive mode 0 0 0 x 1 active (high-speed) mode ? 0 1 0 x 1 active (medium-speed) mode ? 01111active(medium-speed) mode ? 1x111s ubactive mode (direct transition) ? 00111active(high-speed)mode (direct transition) ? [legend] x: don?t care.
rev. 4.00, 03/04, page 109 of 462 table 5.3 internal state in each operating mode active mode sleep mode function high- speed medium- speed high- speed medium- speed watch mode subac- tive mode subsleep mode stand-by mode system clock oscil- lator func- tioning func- tioning func- tioning func- tioning halted halted halted halted subclock oscillator func- tioning func- tioning func- tioning func- tioning func- tioning func- tioning func- tioning func- tioning instruc- tions func- tioning func- tioning halted halted halted func- tioning halted halted ram registers retained retained retained retained retained cpu i/o re- tained * 1 irq0 func- tioning func- tioning func- tioning func- tioning func- tioning func- tioning func- tioning irq1 func- tioning irqaec re- tained * 5 re- tained * 5 external interrupts wkp7 to wkp0 func- tioning func- tioning timer a func- tioning func- tioning func- tioning func- tioning func- tioning * 4 func- tioning * 4 func- tioning * 4 retained asyn- chronous counter func- tioning * 6 func- tioning func- tioning func- tioning * 6 timer f function- ing/reta- ined * 7 function- ing/reta- ined * 7 function- ing/reta- ined * 7 retained wdt function- ing/reta- ined * 9 function- ing/reta- ined * 8 function- ing/reta- ined * 9 function- ing/reta- ined * 10 sci3 func- tioning func- tioning func- tioning func- tioning reset function- ing/reta- ined * 2 function- ing/reta- ined * 2 reset periph- eral modules pwm func- tioning func- tioning func- tioning func- tioning retained retained retained retained
rev. 4.00, 03/04, page 110 of 462 active mode sleep mode function high- speed medium- speed high- speed medium- speed watch mode subac- tive mode subsleep mode stand-by mode a/d con- verter func- tioning func- tioning func- tioning func- tioning retained retained retained retained periph- eral modules lcd func- tioning func- tioning func- tioning func- tioning function- ing/reta- ined * 3 function- ing/reta- ined * 3 function- ing/reta- ined * 3 retained lvd func- tioning func- tioning func- tioning func- tioning func- tioning func- tioning func- tioning func- tioning notes: 1. register contents are retained. output is the high-impedance state. 2. functioning if w /2 is selected as an internal clock, or halted and retained otherwise. 3. functioning if w, w/2, or w/4 is selected as a clock to be used. halted and retained otherwise. 4. functioning if the timekeeping time-base function is selected. 5. an external interrupt request is ignored. contents of the interrupt request register are not affected. 6. the counter can be incremented. an interrupt cannot occur. 7. functioning if w/4 is selected as an internal clock. halted and retained otherwise. 8. on the h8/38104 group, operates when w/32 is selected as the internal clock or the on-chip oscillator is selected; otherwise stops and stands by. on the h8/38004 group, operates when w/32 is selected as the internal clock; otherwise stops and stands by. 9. on the h8/38104 group, operates when w/32 is selected as the internal clock or the on-chip oscillator is selected; otherwise stops and stands by. on the h8/38004 group, stops and stands by. 10. on the h8/38104 group, operates only when the on-chip oscillator is selected; other- wise stops and stands by. on the h8/38004 group, stops and stands by. 5.2.1 sleep mode in sleep mode, cpu operation is halted but the system clock oscillator, subclock oscillator, and on-chip peripheral modules function. in sleep (medium-speed) mode, the on-chip peripheral mod- ules function at the clock frequency set by the ma1 and ma0 bits in syscr1. cpu register con- tents are retained. sleep mode is cleared by an interrupt. when an interrupt is requested, sleep mode is cleared and interrupt exception handling starts. sleep mode is not cleared if the i bit in ccr is set to 1 or the requested interrupt is disabled by the interrupt enable bit. after sleep mode is cleared, a transition is made from sleep (high-speed) mode to active (high-speed) mode or from sleep (medium-speed) mode to active (medium-speed) mode. when the res pin goes low, the cpu goes into the reset state and sleep mode is cleared. since an interrupt request signal is synchronous with the system clock, the maximum time of 2/ (s) may be
rev. 4.00, 03/04, page 111 of 462 delayed from the point at which an interrupt request signal occurs until the interrupt exception handling is started. furthermore, it sometimes operates with half state early timing at the time of transition to sleep (medium-speed) mode. 5.2.2 standby mode in standby mode, the clock pulse generator stops, so the cpu and on-chip peripheral modules stop functioning. however, as long as the rated voltage is supplied, the contents of cpu registers, on- chip ram, and some on-chip peripheral module registers are retained. on-chip ram contents will be retained as long as the voltage set by the ram data retention voltage is provided. the i/o ports go to the high-impedance state. standby mode is cleared by an interrupt. when an interrupt is requested, the system clock pulse generator starts. after the time set in bits sts2 to sts0 in syscr1 has elapsed, standby mode is cleared and interrupt exception handling starts. after standby mode is cleared, a transition is made to active (high-speed) or active (medium-speed) mode according to the mson bit in syscr2. standby mode is not cleared if the i bit in ccr is set to 1 or the requested interrupt is disabled by the interrupt enable bit. when the res pin goes low, the system clock pulse generator starts. since system clock signals are supplied to the entire chip as soon as the system clock pulse generator starts functioning, the res pin must be kept low until the pulse generator output stabilizes. after the pulse generator output has stabilized, the cpu starts reset exception handling if the res pin is driven high. 5.2.3 watch mode in watch mode, the system clock oscillator and cpu operation stop and on-chip peripheral mod- ules stop functioning except for the timer a, timer f, asynchronous event counter, and lcd con- troller/driver. however, as long as the rated voltage is supplied, the contents of cpu registers, some on-chip peripheral module registers, and on-chip ram are retained. the i/o ports retain their state before the transition. watch mode is cleared by an interrupt. when an interrupt is requested, watch mode is cleared and interrupt exception handling starts. when watch mode is cleared by an interrupt, a transition is made to active (high-speed) mode, active (medium-speed) mode, or subactive mode depending on the settings of the lson bit in syscr1 and the mson bit in syscr2. when the transition is made to active mode, after the time set in bits sts2 to sts0 in syscr1 has elapsed, interrupt exception handling starts. watch mode is not cleared if the i bit in ccr is set to 1 or the requested interrupt is disabled by the interrupt enable bit. when the res pin goes low, the system clock pulse generator starts. since system clock signals are supplied to the entire chip as soon as the system clock pulse generator starts functioning, the
rev. 4.00, 03/04, page 112 of 462 res pin must be kept low until the pulse generator output stabilizes. after the pulse generator output has stabilized, the cpu starts reset exception handling if the res pin is driven high. 5.2.4 subsleep mode in subsleep mode, the cpu operation stops but on-chip peripheral modules other than the a/d converter and pwm function. as long as a required voltage is applied, the contents of cpu regis- ters, the on-chip ram, and some registers of the on-chip peripheral modules are retained. i/o ports keep the same states as before the transition. subsleep mode is cleared by an interrupt. when an interrupt is requested, subsleep mode is cleared and interrupt exception handling starts. after subsleep mode is cleared, a transition is made to subactive mode. subsleep mode is not cleared if the i bit in ccr is set to 1 or the requested inter- rupt is disabled in the interrupt enable register. when the res pin goes low, the system clock pulse generator starts. since system clock signals are supplied to the entire chip as soon as the system clock pulse generator starts functioning, the res pin must be kept low until the pulse generator output stabilizes. after the pulse generator output has stabilized, the cpu starts reset exception handling if the res pin is driven high. 5.2.5 subactive mode in subactive mode, the system clock oscillator stops but on-chip peripheral modules other than the a/d converter and pwm function. as long as a required voltage is applied, the contents of some registers of the on-chip peripheral modules are retained. subactive mode is cleared by the sleep instruction. when subacitve mode is cleared, a transition to subsleep mode, active mode, or watch mode is made, depending on the combination of bits ssby and lson in syscr1, bits mson and dton in syscr2, and bit tma3 in tma. subactive mode is not cleared if the i bit in ccr is set to 1 or the requested interrupt is disabled in the interrupt enable register. when the res pin goes low, the system clock pulse generator starts. since system clock signals are supplied to the entire chip as soon as the system clock pulse generator starts functioning, the res pin must be kept low until the pulse generator output stabilizes. after the pulse generator output has stabilized, the cpu starts reset exception handling if the res pin is driven high. the operating frequency of subactive mode is selected from w /2, w /4, and w /8 by the sa1 and sa0 bits in syscr2. after the sleep instruction is executed, the operating frequency changes to the frequency which is set before the execution.
rev. 4.00, 03/04, page 113 of 462 5.2.6 active (medium-speed) mode in active (medium-speed) mode, the system clock oscillator, subclock oscillator, cpu, and on-chip peripheral modules function. active (medium-speed) mode is cleared by the sleep instruction. when active (medium-speed) mode is cleared, a transition to standby mode is made depending on the combination of bits ssby and lson in syscr1 and bit tma3 in tma, a transition to watch mode is made depending on the combination of bit ssby in syscr1 and bit tma3 in tma, or a transition to sleep mode is made depending on the combination of bits ssby and lson in syscr1. moreover, a transition to active (high-speed) mode or subactive mode is made by a direct transition. active (medium- sleep) mode is not entered if the i bit in ccr is set to 1 or the requested interrupt is disabled in the interrupt enable register. when the res pin goes low, the cpu goes into the reset state and active (medium-sleep) mode is cleared. furthermore, it sometimes operates with half state early timing at the time of transition to active (medium-speed) mode. in active (medium-speed) mode, the on-chip peripheral modules function at the clock frequency set by the ma1 and ma0 bits in syscr1. 5.3 direct transition the cpu can execute programs in two modes: active and subactive mode. a direct transition is a transition between these two modes without stopping program execution. a direct transition can be made by executing a sleep instruction while the dton bit in syscr2 is set to 1. the direct transition also enables operating frequency modification in active or subactive mode. after the mode transition, direct transition interrupt exception handling starts. if the direct transition interrupt is disabled in interrupt permission register 2, a transition is made instead to sleep or watch mode. note that if a direct transition is attempted while the i bit in ccr is set to 1, sleep or watch mode will be entered, and the resulting mode cannot be cleared by means of an interrupt. ? direct transfer from active (high-speed) mode to active (medium-speed) mode when a sleep instruction is executed in active (high-speed) mode while the ssby and lson bits in syscr1 are cleared to 0, the mson bit in syscr2 is set to 1, and the dton bit in syscr2 is set to 1, a transition is made to active (medium-speed) mode via sleep mode. ? direct transfer from active (medium-speed) mode to active (high-speed) mode when a sleep instruction is executed in active (medium-speed) mode while the ssby and lson bits in syscr1 are cleared to 0, the mson bit in syscr2 is cleared to 0, and the dton bit in syscr2 is set to 1, a transition is made to active (high-speed) mode via sleep mode.
rev. 4.00, 03/04, page 114 of 462 ? direct transfer from active (high-speed) mode to subactive mode when a sleep instruction is executed in active (high-speed) mode while the ssby and lson bits in syscr1 are set to 1, the dton bit in syscr2 is set to 1, and the tma3 bit in tma is set to 1, a transition is made to subactive mode via watch mode. ? direct transfer from subactive mode to active (high-speed) mode when a sleep instruction is executed in subactive mode while the ssby bit in syscr1 is set to 1, the lson bit in syscr1 is cleared to 0, the mson bit in syscr2 is cleared to 0, the dton bit in syscr2 is set to 1, and the tma3 bit in tma is set to 1, a transition is made directly to active (high-speed) mode via watch mode after the waiting time set in bits sts2 to sts0 in syscr1 has elapsed. ? direct transfer from active (medium-speed) mode to subactive mode when a sleep instruction is executed in active (medium-speed) while the ssby and lson bits in syscr1 are set to 1, the dton bit in syscr2 is set to 1, and the tma3 bit in tma is set to 1, a transition is made to subactive mode via watch mode. ? direct transfer from subactive mode to active (medium-speed) mode when a sleep instruction is executed in subactive mode while the ssby bit in syscr1 is set to 1, the lson bit in syscr1 is cleared to 0, the mson bit in syscr2 is set to 1, the dton bit in syscr2 is set to 1, and the tma3 bit in tma is set to 1, a transition is made di- rectly to active (medium-speed) mode via watch mode after the waiting time set in bits sts2 to sts0 in syscr1 has elapsed. 5.3.1 direct transition from active (high-speed) mode to active (medium-speed) mode the time from the start of sleep instruction execution to the end of interrupt exception handling (the direct transition time) is calculated by equation (1). direct transition time = {(number of sleep instruction execution states) + (number of internal processing states)} (tcyc before transition) + (number of interrupt ex- ception handling execution states) (tcyc after transition) ???????(1) example: direct transition time = (2 + 1) 2tosc + 14 16tosc = 230tosc (when /8 is selected as the cpu operating clock) [legend] tosc: osc clock cycle time tcyc: system clock ( ) cycle time
rev. 4.00, 03/04, page 115 of 462 5.3.2 direct transition from active (medium-speed) mode to active (high-speed) mode the time from the start of sleep instruction execution to the end of interrupt exception handling (the direct transition time) is calculated by equation (2). direct transition time = {(number of sleep instruction execution states) + (number of internal processing states)} (tcyc before transition) + (number of interrupt ex- ception handling execution states) (tcyc after transition) ??????..(2) example: direct transition time = (2 + 1) 16tosc + 14 2tosc = 76tosc (when /8 is se- lected as the cpu operating clock) [legend] tosc: osc clock cycle time tcyc: system clock ( ) cycle time 5.3.3 direct transition from subactive mode to active (high-speed) mode the time from the start of sleep instruction execution to the end of interrupt exception handling (the direct transition time) is calculated by equation (3). direct transition time = {(number of sleep instruction execution states) + (number of internal processing states)} (tsubcyc before transition) + {(wait time set in bits sts2 to sts0) + (number of interrupt exception handling execution states)} (tcyc after transition) ??????..(3) example: direct transition time = (2 + 1) 8tw + (8192 + 14) 2tosc = 24tw + 16412tosc (when w/8 is selected as the cpu operating clock and wait time = 8192 states) [legend] tosc: osc clock cycle time tw: watch clock cycle time tcyc: system clock ( ) cycle time tsubcyc: subclock ( sub ) cycle time
rev. 4.00, 03/04, page 116 of 462 5.3.4 direct transition from subactive mode to active (medium-speed) mode the time from the start of sleep instruction execution to the end of interrupt exception handling (the direct transition time) is calculated by equation (4). direct transition time = {(number of sleep instruction execution states) + (number of internal processing states)} (tsubcyc before transition) + {(wait time set in bits sts2 to sts0) + (number of interrupt exception handling execution states)} (tcyc after transition) ??????..(4) example: direct transition time = (2 + 1) 8tw + (8192 + 14) 16tosc = 24tw + 131296tosc (when w/8 or /8 is selected as the cpu operating clock and wait time = 8192 states) [legend] tosc: osc clock cycle time tw: watch clock cycle time tcyc: system clock ( ) cycle time tsubcyc: subclock ( sub ) cycle time 5.3.5 notes on external input signal changes before/after direct transition ? direct transition from active (high-speed) mode to subactive mode since the mode transition is performed via watch mode, see section 5.5.2, notes on external input signal changes before/after standby mode. ? direct transition from active (medium-speed) mode to subactive mode since the mode transition is performed via watch mode, see section 5.5.2, notes on external input signal changes before/after standby mode. ? direct transition from subactive mode to active (high-speed) mode since the mode transition is performed via watch mode, see section 5.5.2, notes on external input signal changes before/after standby mode. ? direct transition from subactive mode to active (medium-speed) mode since the mode transition is performed via watch mode, see section 5.5.2, notes on external input signal changes before/after standby mode.
rev. 4.00, 03/04, page 117 of 462 5.4 module standby function the module-standby function can be set to any peripheral module. in module standby mode, the clock supply to modules stops to enter the power-down mode. module standby mode enables each on-chip peripheral module to enter the standby state by clearing a bit that corresponds to each moduleinckstpr1andckstpr2to0andcancelsthemodebysettingthebitto1.(seesection 5.1.3, clock halt registers 1 and 2 (ckstpr1 and ckstpr2).) 5.5 usage notes 5.5.1 standby mode transition and pin states when a sleep instruction is executed in active (high-speed) mode or active (medium-speed) mode while bit ssby is set to 1 and bit lson is cleared to 0 in syscr1, and bit tma3 is cleared to 0 in tma, a transition is made to standby mode. at the same time, pins go to the high- impedance state (except pins for which the pull-up mos is designated as on). figure 5.2 shows the timing in this case. sleep instruction fetch internal data bus next instruction fetch port output pins high-impedance active (high-speed) mode or active (medium-speed) mode standby mode sleep instruction execution internal processing figure 5.2 standby mode transition and pin states 5.5.2 notes on external input signal changes before/after standby mode 1. when external input signal changes before/after standby mode or watch mode when an external input signal such as irq , wkp , or irqaec is input, both the high- and low-level widths of the signal must be at least two cycles of system clock or subclock sub (referred to together in this section as the internal clock). as the internal clock stops in standby mode and watch mode, the width of external input signals requires careful attention when a transition is made via these operating modes. ensure that external input signals conform to the conditions stated in 3, recommended timing of external input signals, below. 2. when external input signals cannot be captured because internal clock stops the case of falling edge capture is shown in figure 5.3.
rev. 4.00, 03/04, page 118 of 462 as shown in the case marked "capture not possible," when an external input signal falls im- mediately after a transition to active (high-speed or medium-speed) mode or subactive mode, after oscillation is started by an interrupt via a different signal, the external input signal cannot be captured if the high-level width at that point is less than 2 tcyc or 2 tsubcyc . 3. recommended timing of external input signals to ensure dependable capture of an external input signal, high- and low-level signal widths of at least 2 tcyc or 2 tsubcyc are necessary before a transition is made to standby mode or watch mode, as shown in "capture possible: case 1." external input signal capture is also possible with the timing shown in "capture possible: case 2" and "capture possible: case 3," in which a 2 tcyc or 2 tsubcyc level width is secured. tcyc tsubcyc tcyc tsubcyc tcyc tsubcyc tcyc tsubcyc capture possible: case 1 capture possible: case 2 capture possible: case 3 capture not possible figure 5.3 external input signal capture when signal changes before/after standby mode or watch mode 4. input pins to which these notes apply: irq1 , irq0 , wkp7 to wkp0 ,andirqaec
rom3322a_000020020900 rev. 4.00, 03/04, page 119 of 462 section 6 rom the h8/3802 has 16 kbytes of the on-chip mask rom, the h8/3801 has 12 kbytes, and the h8/3800 has 8 kbytes. the h8/38004 and h8/38104 have 32 kbytes of the on-chip mask rom, the h8/38003 and h8/38103 have 24 kbytes, the h8/38002 and h8/38102 have 16 kbytes, the h8/38001 and h8/38101 have 12 kbytes, and the h8/38000 and h8/38100 have 8 kbytes. the rom is connected to the cpu by a 16-bit data bus, allowing high-speed two-state access for both byte data and word data. the h8/3802 has a ztat version with 16-kbyte prom. the h8/38004, h8/38002, h8/38104, and h8/38102 have f-ztat? versions with 32-kbyte flash memory and 16-kbyte flash memory, respectively. 6.1 block diagram figure 6.1 shows a block diagram of the on-chip rom. internal data bus (upper 8 bits) internal data bus (lower 8 bits) h'0000 h'0002 h'3ffe h'0000 h'0002 h'3ffe h'0001 h'0003 h'3fff on-chip rom even address odd address figure 6.1 block diagram of rom (h8/3802)
rev. 4.00, 03/04, page 120 of 462 6.2 h8/3802 prom mode 6.2.1 setting to prom mode if the on-chip rom is prom, setting the chip to prom mode stops operation as a microcomputer and allows the prom to be programmed in the same way as the standard hn27c101 eprom. however, page programming is not supported. table 6.1 shows how to set the chip to prom mode. table 6.1 setting to prom mode pin name setting test high level pb0/an0 pb1/an1 low level pb2/an2 high level 6.2.2 socket adapter pin arrangement and memory map a standard prom programmer can be used to program the prom. a socket adapter is required forconversionto32pins. figure 6.2 shows the pin-to-pin wiring of the socket adapter. figure 6.3 shows a memory map.
rev. 4.00, 03/04, page 121 of 462 fp-64a, fp-64e dp-64s pin 8 40 39 38 37 36 35 34 33 57 58 10 11 12 13 14 15 32 60 30 29 28 27 26 52 53 25 31 51 16 61 7 2 64 49 50 54 55 4 62 63 16 48 47 46 45 44 43 42 41 1 2 18 19 20 21 22 23 40 4 38 37 36 35 34 60 61 33 39 59 24 5 15 10 8 57 58 62 63 12 6 7 hn27c101 (32 pins) 1 13 14 15 17 18 19 20 21 12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 2 22 24 31 32 16 p60 p61 p62 p63 p64 p65 p66 p67 p40 p41 p32 p33 p34 p35 p36 p37 p70 p43 p72 p73 p74 p75 p76 p93 p94 p77 p71 p92 vcc avcc test x1 pb2 p90 p91 p95 vss avss pb0 pb1 pin vpp eo0 eo1 eo2 eo3 eo4 eo5 eo6 eo7 ea0 ea1 ea2 ea3 ea4 ea5 ea6 ea7 ea8 ea9 ea10 ea11 ea12 ea13 ea14 ea15 ea16 vcc vss note: pins not shown in the figure should be open. h8/3802 eprom socket figure 6.2 socket adapter pin correspondence (with hn27c101)
rev. 4.00, 03/04, page 122 of 462 address in mcu mode address in prom mode h'0000 h'0000 h'1ffff h'3fff h'3fff on-chip prom uninstalled area * note: * the output data is not guaranteed if this address area is read in prom mode. therefore, when programming with a prom programmer, be sure to specify addresses from h'0000 to h'3fff. if programming is inadvertently performed from h'4000 onward, it may not be possible to continue prom programming and verification. when programming, h'ff should be set as the data in this address area (h'4000 to h'1ffff). figure 6.3 h8/3802 memory map in prom mode
rev. 4.00, 03/04, page 123 of 462 6.3 h8/3802 programming the write, verify, and other modes are selected as shown in table 6.2 in h8/3802 prom mode. table 6.2 mode selection in prom mode (h8/3802) pins mode ce ce ce ce oe oe oe oe pgm pgm pgm pgm vpp vcc eo7 to eo0 ea16 to ea0 write l h l vpp vcc data input address input verify l l h vpp vcc data output address input lll lhh hl l programming disabled hhh vpp vcc high impedance address input [legend] l: low level h: high level vpp: vpp level vcc: vcc level the specifications for writing and reading are identical to those for the standard hn27c101 eprom. however, page programming is not supported, and so page programming mode must not be set. a prom programmer that only supports page programming mode cannot be used. when selecting a prom programmer, ensure that it supports high-speed, high-reliability byte-by-byte programming. also, be sure to specify addresses from h'0000 to h'3fff. 6.3.1 writing and verifying an efficient, high-speed, high-reliability method is available for writing and verifying the prom data. this method achieves high speed without voltage stress on the device and without lowering the reliability of written data. the basic flow of this high-speed, high-reliability programming method is shown in figure 6.4.
rev. 4.00, 03/04, page 124 of 462 set write/verify mode v cc = 6.0 v?.25 v, v pp = 12.5 v?.3 v start address = 0 n = 0 n + 1 n write time tpw = 0.2 ms?% verify write time topw = 0.2n ms last address? set read mode v cc = 5.0 v?.25 v, v pp = v cc read all addresses? error end address + 1 address n < 25 no no yes yes yes yes no no figure 6.4 high-speed, high-reliability programming flowchart table 6.3 and table 6.4 give the electrical characteristics in programming mode.
rev. 4.00, 03/04, page 125 of 462 table 6.3 dc characteristics (conditions: vcc = 6.0 v 0.25 v, vpp = 12.5 v 0.3 v, vss = 0 v, ta = 25c 5c) item symbol min typ max unit test condition input high- level voltage eo7 to eo0, ea16 to ea0, oe , ce , pgm v ih 2.4 ? vcc + 0.3 v input low-level voltage eo7 to eo0, ea16 to ea0, oe , ce , pgm v il ?0.3 ? 0.8 v output high- level voltage eo7 to eo0 v oh 2.4 ? ? v i oh = ?200 a output low- level voltage eo7 to eo0 v ol ? ? 0.45 v i ol =0.8ma input leakage current eo7 to eo0, ea16 to ea0, oe , ce , pgm |i li |? ?2 av in = 5.25 v/0.5 v vcc current i cc ??40 ma vpp current i pp ??40 ma
rev. 4.00, 03/04, page 126 of 462 table 6.4 ac characteristics (conditions: vcc = 6.0 v 0.25 v, vpp = 12.5 v 0.3 v, ta = 25c 5c) item symbol min typ max unit test condition address setup time t as 2??s oe setup time t oes 2??s data setup time t ds 2??s address hold time t ah 0??s data hold time t dh 2??s data output disable time t df * 2 ? ? 130 s vpp setup time t vps 2??s programming pulse width t pw 0.19 0.20 0.21 ms pgm pulse width for overwrite programming t opw * 3 0.19 ? 5.25 ms ce setup time t ces 2??s vcc setup time t vcs 2??s data output delay time t oe 0 ? 200 ns figure 6.5 * 1 notes: 1. input pulse level: 0.45 v to 2.4 v input rise time/fall time 20 ns timing reference levels input: 0.8 v, 2.0 v output: 0.8 v, 2.0 v 2. t df is defined at the point at which the output is floating and the output level cannot be read. 3. t opw is defined by the value given in figure 6.4, high-speed, high-reliability programming flow chart. figure 6.5 shows a prom write/verify timing.
rev. 4.00, 03/04, page 127 of 462 write input data output data verify address data v pp v pp t as t ah t ds t dh t df t oe t oes t pw t opw * t vps t vcs t ces v cc v cc v cc +1 v cc note: * t opw is defined by the value shown in figure 6.4, high-speed, high-reliability programming flowchart. figure 6.5 prom write/verify timing 6.3.2 programming precautions ? use the specified programming voltage and timing. the programming voltage in prom mode (vpp) is 12.5 v. use of a higher voltage can permanently damage the chip. be especially careful with respect to prom programmer overshoot. setting the prom programmer to renesas (former hitachi) specifications for the hn27c101 will result in correct vpp of 12.5 v. ? make sure the index marks on the prom programmer socket, socket adapter, and chip are properly aligned. if they are not, the chip may be destroyed by excessive current flow. before programming, be sure that the chip is properly mounted in the prom programmer. ? avoid touching the socket adapter or chip while programming, since this may cause contact faults and write errors. ? take care when setting the programming mode, as page programming is not supported. ? when programming with a prom programmer, be sure to specify addresses from h'0000 to h'3fff. if programming is inadvertently performed from h'4000 onward, it may not be
rev. 4.00, 03/04, page 128 of 462 possible to continue prom programming and verification. when programming, h'ff should be set as the data in address area h'4000 to h'1ffff. 6.4 reliability of programmed data a highly effective way to improve data retention characteristics is to bake the programmed chips at 150c, then screen them for data errors. this procedure quickly eliminates chips with prom memory cells prone to early failure. figure 6.6 shows the recommended screening procedure. program chip and verify programmed data bake chip for 24 to 48 hours at 125?c to 150?c with power off read and check program install figure 6.6 recommended screening procedure if a group of programming errors occurs while the same prom programmer is in use, stop programming and check the prom programmer and socket adapter for defects. please inform renesas of any abnormal conditions noted during or after programming or in screening of program data after high-temperature baking.
rev. 4.00, 03/04, page 129 of 462 6.5 overview of flash memory 6.5.1 features the features of the 32-kbyte or 16-kbyte flash memory built into the flash memory version are summarized below. ? programming/erase methods ? the flash memory is programmed 128 bytes at a time. erase is performed in single-block units. the flash memory of the hd64f38004 and hd64f38104 are configured as follows: 1kbyte 4 blocks and 28 kbytes 1 block. the flash memory of the hd64f38002 and hd64f38102 are configured as follows: 1 kbyte 4 blocks and 12 kbytes 1block.to erase the entire flash memory, each block must be erased in turn. ? on-board programming ? on-board programming/erasing can be done in boot mode, in which the boot program built into the chip is started to erase or program of the entire flash memory. in normal user program mode, individual blocks can be erased or programmed. ? programmer mode ? flash memory can be programmed/erased in programmer mode using a prom programmer, as well as in on-board programming mode. ? automatic bit rate adjustment ? for data transfer in boot mode, this lsi's bit rate can be automatically adjusted to match the transfer bit rate of the host. ? programming/erasing protection ? sets software protection against flash memory programming/erasing. ? power-down mode ? operation of the power supply circuit can be partly halted in subactive mode. as a result, flash memory can be read with low power consumption. note: the system clock oscillator must be used when programming or erasing the flash memory of the hd64f38104 and hd64f38102.
rev. 4.00, 03/04, page 130 of 462 6.5.2 block diagram internal address bus internal data bus (16 bits) flmcr1 bus interface/controller operating mode test pin p95 pin p34 pin [legend] flmcr1: flash memory control register 1 flmcr2: flash memory control register 2 ebr: erase block register flpwcr: flash memory power control register fenr: flash memory enable register flmcr2 ebr flpwcr fenr module bus flash memory figure 6.7 block diagram of flash memory
rev. 4.00, 03/04, page 131 of 462 6.5.3 block configuration figure 6.8 shows the block configuration of 32-kbyte flash memory. the thick lines indicate erasing units, the narrow lines indicate programming units, and the values are addresses. the 32- kbyte flash memory is divided into 1 kbyte 4 blocks and 28 kbytes 1block.erasingis performed in these units. the 16-kbyte flash memory is divided into 1 kbyte 4blocksand12 kbytes 1 block. programming is performed in 128-byte units starting from an address with lower eight bits h'00 or h'80. h'007f h'0000 h'0001 h'0002 h'00ff h'0080 h'0081 h'0082 h'03ff h'0380 h'0381 h'0382 h'047f h'0400 h'0401 h'0402 h'04ff h'0480 h'0481 h'0482 h'07ff h'0780 h'0781 h'0782 h'087f h'0800 h'0801 h'0802 h'08ff h'0880 h'0881 h'0882 h'0bff h'0b80 h'0b81 h'0b82 h'0c7f h'0c00 h'0c01 h'0c02 h'0cff h'0c80 h'0c81 h'0c82 h'0fff h'0f80 h'0f81 h'0f82 h'107f h'1000 h'1001 h'1002 h'10ff h'1080 h'1081 h'1082 h'7fff h'7f80 h'7f81 h'7f82 programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes 1 kbyte erase unit 1 kbyte erase unit 1 kbyte erase unit 1 kbyte erase unit 28 kbytes erase unit figure 6.8(1) block configuration of 32-kbyte flash memory
rev. 4.00, 03/04, page 132 of 462 h'007f h'0000 h'0001 h'0002 h'00ff h'0080 h'0081 h'0082 h'03ff h'0380 h'0381 h'0382 h'047f h'0400 h'0401 h'0402 h'04ff h'0480 h'0481 h'0482 h'07ff h'0780 h'0781 h'0782 h'087f h'0800 h'0801 h'0802 h'08ff h'0880 h'0881 h'0882 h'0bff h'0b80 h'0b81 h'0b82 h'0c7f h'0c00 h'0c01 h'0c02 h'0cff h'0c80 h'0c81 h'0c82 h'0fff h'0f80 h'0f81 h'0f82 h'107f h'1000 h'1001 h'1002 h'10ff h'1080 h'1081 h'1082 h'3fff h'3f80 h'3f81 h'3f82 programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes programming unit: 128 bytes 1 kbyte erase unit 1 kbyte erase unit 1 kbyte erase unit 1 kbyte erase unit 12 kbytes erase unit figure 6.8(2) block configuration of 16-kbyte flash memory 6.6 register descriptions the flash memory has the following registers. ? flash memory control register 1 (flmcr1) ? flash memory control register 2 (flmcr2) ? erase block register (ebr) ? flash memory power control register (flpwcr) ? flash memory enable register (fenr)
rev. 4.00, 03/04, page 133 of 462 6.6.1 flash memory control register 1 (flmcr1) flmcr1 is a register that makes the flash memory change to program mode, program-verify mode, erase mode, or erase-verify mode. for details on register setting, refer to section 6.8, flash memory programming/erasing. bit bit name initial value r/w description 7? 0 ?reserved this bit is always read as 0. 6 swe 0 r/w software write enable when this bit is set to 1, flash memory programming/erasing is enabled. when this bit is cleared to 0, flash memory programming/erasing is invalid. other flmcr1 bits and all ebr bits cannot be set. 5 esu 0 r/w erase setup when this bit is set to 1, the flash memory changes to the erase setup state. when it is cleared to 0, the erase setup state is cancelled. set this bit to 1 before setting the e bit to1inflmcr1. 4 psu 0 r/w program setup when this bit is set to 1, the flash memory changes to the program setup state. when it is cleared to 0, the program setup state is cancelled. set this bit to 1 before setting the p bit in flmcr1. 3 ev 0 r/w erase-verify when this bit is set to 1, the flash memory changes to erase-verify mode. when it is cleared to 0, erase-verify mode is cancelled. 2 pv 0 r/w program-verify when this bit is set to 1, the flash memory changes to program-verify mode. when it is cleared to 0, program- verify mode is cancelled. 1e 0 r/werase when this bit is set to 1, and while the swe = 1 and esu = 1 bits are 1, the flash memory changes to erase mode. when it is cleared to 0, erase mode is cancelled. 0 p 0 r/w program when this bit is set to 1, and while the swe = 1 and psu = 1 bits are 1, the flash memory changes to program mode. when it is cleared to 0, program mode is cancelled. note: bits swe, psu, ev, pv, e, and p should not be set at the same time.
rev. 4.00, 03/04, page 134 of 462 6.6.2 flash memory control register 2 (flmcr2) flmcr2 is a register that displays the state of flash memory programming/erasing. flmcr2 is a read-only register, and should not be written to. bit bit name initial value r/w description 7 fler 0 r flash memory error indicates that an error has occurred during an operation on flash memory (programming or erasing). when flash memory goes to the error-protection state, this bit is set to 1. see section 6.9.3, error protection, for details. 6to0 ? all0 ? reserved these bits are always read as 0. 6.6.3 erase block register (ebr) ebr specifies the flash memory erase area block. ebr is initialized to h'00 when the swe bit in flmcr1 is 0. do not set more than one bit at a time, as this will cause all the bits in ebr to be automatically cleared to 0. bit bit name initial value r/w description 7to5 ? all0 ? reserved these bits are always read as 0. 4 eb4 0 r/w when this bit is set to 1, 28 kbytes of h'1000 to h'7fff will be erased in the hd64f38004 and hd64f38104. when this bit is set to 1, 12 kbytes of h'1000 to h'3fff will be erased in the hd64f38002 and hd64f38102. 3 eb3 0 r/w when this bit is set to 1, 1 kbyte of h'0c00 to h'0fff will be erased. 2 eb2 0 r/w when this bit is set to 1, 1 kbyte of h'0800 to h'0bff will be erased. 1 eb1 0 r/w when this bit is set to 1, 1 kbyte of h'0400 to h'07ff will be erased. 0 eb0 0 r/w when this bit is set to 1, 1 kbyte of h'0000 to h'03ff will be erased.
rev. 4.00, 03/04, page 135 of 462 6.6.4 flash memory power control register (flpwcr) flpwcr enables or disables a transition to the flash memory power-down mode when the lsi switches to subactive mode. there are two modes: mode in which operation of the power supply circuit of flash memory is partly halted in power-down mode and flash memory can be read, and mode in which even if a transition is made to subactive mode, operation of the power supply circuit of flash memory is retained and flash memory can be read. bit bit name initial value r/w description 7 pdwnd 0 r/w power-down disable when this bit is 0 and a transition is made to subactive mode, the flash memory enters the power-down mode. when this bit is 1, the flash memory remains in the normal mode even after a transition is made to subactive mode. 6to0 ? all0 ? reserved these bits are always read as 0. 6.6.5 flash memory enable register (fenr) bit 7 (flshe) in fenr enables or disables the cpu access to the flash memory control registers, flmcr1, flmcr2, ebr, and flpwcr. bit bit name initial value r/w description 7 flshe 0 r/w flash memory control register enable flash memory control registers can be accessed when this bit is set to 1. flash memory control registers cannot be accessed when this bit is set to 0. 6to0 ? all0 ? reserved these bits are always read as 0.
rev. 4.00, 03/04, page 136 of 462 6.7 on-board programming modes there are two modes for programming/erasing of the flash memory; boot mode, which enables on- board programming/erasing, and programmer mode, in which programming/erasing is performed with a prom programmer. on-board programming/erasing can also be performed in user program mode. at reset-start in reset mode, this lsi changes to a mode depending on the test pin settings, p95 pin settings, and input level of each port, as shown in table 6.5. the input level of each pin must be defined four states before the reset ends. when changing to boot mode, the boot program built into this lsi is initiated. the boot program transfers the programming control program from the externally-connected host to on-chip ram via sci3. after erasing the entire flash memory, the programming control program is executed. this can be used for programming initial values in the on-board state or for a forcible return when programming/erasing can no longer be done in user program mode. in user program mode, individual blocks can be erased and programmed by branching to the user program/erase control program prepared by the user. table 6.5 setting programming modes test p95 p34 pb0 pb1 pb2 lsi state after reset end 0 1 xxxxusermode 0 0 1 x x x boot mode 1 x x 0 0 0 programmer mode [legend] x: don?t care. 6.7.1 boot mode table 6.6 shows the boot mode operations between reset end and branching to the programming control program. 1. when boot mode is used, the flash memory programming control program must be prepared in the host beforehand. prepare a programming control program in accordance with the description in section 6.8, flash memory programming/erasing. 2. the sci3 should be set to asynchronous mode, and the transfer format as follows: 8-bit data, 1 stop bit, and no parity. since the inversion function of spcr is configured not to inverse data of the txd pin and rxd pin, do not place an inversion circuit between the host and this lsi. 3. when the boot program is initiated, the chip measures the low-level period of asynchronous sci communication data (h'00) transmitted continuously from the host. the chip then calculates the bit rate of transmission from the host, and adjusts the sci3 bit rate to match that of the host. the reset should end with the rxd pin high. the rxd and txd pins should be pulled up on the board if necessary. after the reset is complete, it takes approximately 100 states before the chip is ready to measure the low-level period.
rev. 4.00, 03/04, page 137 of 462 4. after matching the bit rates, the chip transmits one h'00 byte to the host to indicate the completion of bit rate adjustment. the host should confirm that this adjustment end indication (h'00) has been received normally, and transmit one h'55 byte to the chip. if reception could not be performed normally, initiate boot mode again by a reset. depending on the host's transfer bit rate and system clock frequency of this lsi, there will be a discrepancy between the bit rates of the host and the chip. to operate the sci properly, set the host's transfer bit rate and system clock frequency of this lsi within the ranges listed in table 6.7. 5. in boot mode, a part of the on-chip ram area is used by the boot program. the area h'f780 to h'feef is the area to which the programming control program is transferred from the host. the boot program area cannot be used until the execution state in boot mode switches to the programming control program. 6. before branching to the programming control program, the chip terminates transfer operations by sci3 (by clearing the re and te bits in scr to 0), however the adjusted bit rate value remains set in brr. therefore, the programming control program can still use it for transfer of write data or verify data with the host. the txd pin is high (pcr42 = 1, p42 = 1). the contents of the cpu general registers are undefined immediately after branching to the programming control program. these registers must be initialized at the beginning of the programming control program, as the stack pointer (sp), in particular, is used implicitly in subroutine calls, etc. 7. boot mode can be cleared by a reset. end the reset after driving the reset pin low, waiting at least 20 states, and then setting the test pin and p95 pin. boot mode is also cleared when a wdt overflow occurs. 8. do not change the test pin and p95 pin input levels in boot mode.
rev. 4.00, 03/04, page 138 of 462 table 6.6 boot mode operation communication contents processing contents host operation lsi operation processing contents continuously transmits data h'00 at specified bit rate. branches to boot program at reset-start. boot program initiation h'00, h'00 . . . h'00 h'00 h'55 transmits data h'55 when data h'00 is received error-free. h'xx transmits number of bytes (n) of programming control program to be transferred as 2-byte data (low-order byte following high-order byte) transmits 1-byte of programming control program (repeated for n times) h'aa reception h'aa reception upper bytes, lower bytes echoback echoback h'aa h'aa branches to programming control program transferred to on-chip ram and starts execution. transmits data h'aa to host. checks flash memory data, erases all flash memory blocks in case of written data existing, and transmits data h'aa to host. (if erase could not be done, transmits data h'ff to host and aborts operation.) h'ff boot program erase error item boot mode initiation measures low-level period of receive data h'00. calculates bit rate and sets brr in sci3. transmits data h'00 to host as adjustment end indication. bit rate adjustment echobacks the 2-byte data received to host. echobacks received data to host and also transfers it to ram. (repeated for n times) transfer of number of bytes of programming control program flash memory erase
rev. 4.00, 03/04, page 139 of 462 table 6.7 oscillation frequencies for which automatic adjustment of lsi bit rate is possible (f osc ) product group host bit rate oscillation frequency range of lsi (f osc ) 4,800 bps 8 to 10 mhz h8/38004f group 2,400 bps 4 to 10 mhz 1,200 bps 2 to 10 mhz h8/38104f group 19,200 bps 16 mhz 9,600 bps 8 to 16 mhz 4,800 bps 4 to 16 mhz 2,400 bps 2 to 16 mhz 1,200 bps 2 to 16 mhz 6.7.2 programming/erasing in user program mode user program mode means the execution state of the user program. on-board programming/erasing of an individual flash memory block can also be performed in user program mode by branching to a user program/erase control program. the user must set branching conditions and provide on-board means of supplying programming data. the flash memory must contain the user program/erase control program or a program that provides the user program/erase control program from external memory. as the flash memory itself cannot be read during programming/erasing, transfer the user program/erase control program to on-chip ram, as in boot mode. figure 6.9 shows a sample procedure for programming/erasing in user program mode. prepare a user program/erase control program in accordance with the description in section 6.8, flash memory programming/erasing.
rev. 4.00, 03/04, page 140 of 462 ye s no program/erase? transfer user program/erase control program to ram reset-start branch to user program/erase control program in ram execute user program/erase control program (flash memory rewrite) branch to flash memory application program branch to flash memory application program figure 6.9 programming/erasing flowchart example in user program mode 6.7.3 notes on on-board programming 1. you must use the system clock oscillator when programming or erasing flash memory on the h8/38104f group. the on-chip oscillator should not be used for programming or erasing flash memory. see section 4.3.4, on-chip oscillator selection method, for information on switching between the system clock oscillator and the on-chip oscillator. 2. on the h8/38104f group the watchdog timer operates after a reset is canceled. when executing a program prepared by the user that performs programming and erasing in the user mode, the watchdog timer?s overflow cycle should be set to an appropriate value. refer to section 6.8.1, program/program-verify, for information on the appropriate watchdog timer overflow cycle for programming, and to 6.8.2, erase/erase-verify, for information on the appropriate watchdog timer overflow cycle for erasing.
rev. 4.00, 03/04, page 141 of 462 6.8 flash memory programming/erasing a software method using the cpu is employed to program and erase flash memory in the on- board programming modes. depending on the flmcr1 setting, the flash memory operates in one of the following four modes: program mode, program-verify mode, erase mode, and erase-verify mode. the programming control program in boot mode and the user program/erase control program in user program mode use these operating modes in combination to perform programming/erasing. flash memory programming and erasing should be performed in accordance with the descriptions in section 6.8.1, program/program-verify and section 6.8.2, erase/erase-verify, respectively. 6.8.1 program/program-verify when writing data or programs to the flash memory, the program/program-verify flowchart shown in figure 6.10 should be followed. performing programming operations according to this flowchart will enable data or programs to be written to the flash memory without subjecting the chip to voltage stress or sacrificing program data reliability. 1. programming must be done to an empty address. do not reprogram an address to which programming has already been performed. 2. programming should be carried out 128 bytes at a time. a 128-byte data transfer must be performed even if writing fewer than 128 bytes. in this case, h'ff data must be written to the extra addresses. 3. prepare the following data storage areas in ram: a 128-byte programming data area, a 128- byte reprogramming data area, and a 128-byte additional-programming data area. perform reprogramming data computation according to table 6.8, and additional programming data computation according to table 6.9. 4. consecutively transfer 128 bytes of data in byte units from the reprogramming data area or additional-programming data area to the flash memory. the program address and 128-byte data are latched in the flash memory. the lower 8 bits of the start address in the flash memory destination area must be h'00 or h'80. 5. the time during which the p bit is set to 1 is the programming time. table 6.10 shows the allowable programming times. 6. the watchdog timer (wdt) is set to prevent overprogramming due to program runaway, etc. an overflow cycle of approximately 6.6 ms is allowed. 7. for a dummy write to a verify address, write 1-byte data h'ff to an address whose lower one bit is b'0. verify data can be read in word units from the address to which a dummy write was performed. 8. the maximum number of repetitions of the program/program-verify sequence of the same bit is 1,000.
rev. 4.00, 03/04, page 142 of 462 start end of programming set swe bit in flmcr1 write pulse application subroutine wait 1 figure 6.10 program/program-verify flowchart
rev. 4.00, 03/04, page 143 of 462 table 6.8 reprogram data computation table program data verify data reprogram data comments 0 0 1 programming completed 0 1 0 reprogram bit 10 1 ? 1 1 1 remains in erased state table 6.9 additional-program data computation table reprogram data verify data additional-program data comments 0 0 0 additional-program bit 0 1 1 no additional programming 1 0 1 no additional programming 1 1 1 no additional programming table 6.10 programming time n (number of writes) programming time in additional programming comments 1to6 30 10 7 to 1,000 200 ? note: time shown in s.
rev. 4.00, 03/04, page 144 of 462 6.8.2 erase/erase-verify when erasing flash memory, the erase/erase-verify flowchart shown in figure 6.11 should be followed. 1. prewriting (setting erase block data to all 0s) is not necessary. 2. erasing is performed in block units. make only a single-bit specification in the erase block register (ebr). to erase multiple blocks, each block must be erased in turn. 3. the time during which the e bit is set to 1 is the flash memory erase time. 4. the watchdog timer (wdt) is set to prevent overerasing due to program runaway, etc. an overflow cycle of approximately 19.8 ms is allowed. 5. for a dummy write to a verify address, write 1-byte data h'ff to an address whose lower 1 bit is b'0. verify data can be read in word units from the address to which a dummy write was performed. 6. if the read data is not erased successfully, set erase mode again, and repeat the erase/erase- verify sequence as before. the maximum number of repetitions of the erase/erase-verify sequence is 100. 6.8.3 interrupt handling when programming/erasing flash memory all interrupts, including the nmi interrupt, are disabled while flash memory is being programmed or erased, or while the boot program is executing, for the following three reasons: 1. interrupt during programming/erasing may cause a violation of the programming or erasing algorithm, with the result that normal operation cannot be assured. 2. if interrupt exception handling starts before the vector address is written or during programming/erasing, a correct vector cannot be fetched and the cpu malfunctions. 3. if an interrupt occurs during boot program execution, normal boot mode sequence cannot be carried out.
rev. 4.00, 03/04, page 145 of 462 erase start set ebr enable wdt wait 1 figure 6.11 erase/erase-verify flowchart
rev. 4.00, 03/04, page 146 of 462 6.9 program/erase protection there are three kinds of flash memory program/erase protection; hardware protection, software protection, and error protection. 6.9.1 hardware protection hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted because of a transition to reset, subactive mode, subsleep mode, watch mode, or standby mode. flash memory control register 1 (flmcr1), flash memory control register 2 (flmcr2), and erase block register (ebr) are initialized. in a reset via the res pin, the reset state is not entered unless the res pin is held low until oscillation stabilizes after powering on. in the case of a reset during operation, hold the res pin low for the res pulse width specified in the ac characteristics section. 6.9.2 software protection software protection can be implemented against programming/erasing of all flash memory blocks by clearing the swe bit in flmcr1. when software protection is in effect, setting the p or e bit in flmcr1 does not cause a transition to program mode or erase mode. by setting the erase block register (ebr), erase protection can be set for individual blocks. when ebr is set to h'00, erase protection is set for all blocks. 6.9.3 error protection in error protection, an error is detected when cpu runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. when the following errors are detected during programming/erasing of flash memory, the fler bit in flmcr2 is set to 1, and the error protection state is entered. ? when the flash memory of the relevant address area is read during programming/erasing (including vector read and instruction fetch) ? immediately after exception handling excluding a reset during programming/erasing ? when a sleep instruction is executed during programming/erasing the flmcr1, flmcr2, and ebr settings are retained, however program mode or erase mode is aborted at the point at which the error occurred. program mode or erase mode cannot be re-entered by re-setting the p or e bit. however, pv and ev bit setting is enabled, and a transition can be made to verify mode. error protection can be cleared only by a power-on reset.
rev. 4.00, 03/04, page 147 of 462 6.10 programmer mode in programmer mode, a prom programmer can be used to perform programming/erasing via a socket adapter, just as a discrete flash memory. use a prom programmer that supports the mcu device type with the on-chip renesas technology (former hitachi ltd.) 64-kbyte flash memory (fztat64v3). a 10-mhz input clock is required. for the conditions for transition to programmer mode, see table 6.5. 6.10.1 socket adapter the socket adapter converts the pin allocation of the hd64f38004, hd64f38002, hd64f38104, and hd64f38102 to that of the discrete flash memory hn28f101. the address of the on-chip flash memory is h'0000 to h'7fff. figure 6.12(1) shows a socket-adapter-pin correspondence diagram of the hd64f38004 and hd64f38002. figure 6.12(2) shows a socket-adapter-pin correspondence of the hd64f38104 and hd64f38102. 6.10.2 programmer mode commands the following commands are supported in programmer mode. ? memory read mode ? auto-program mode ? auto-erase mode ? status read mode status polling is used for auto-programming, auto-erasing, and status read modes. in status read mode, detailed internal information is output after the execution of auto-programming or auto- erasing. table 6.11 shows the sequence of each command. in auto-programming mode, 129 cycles are required since 128 bytes are written at the same time. in memory read mode, the number of cycles depends on the number of address write cycles (n). table 6.11 command sequence in programmer mode 1st cycle 2nd cycle command name number of cycles mode address data mode address data memory read 1 + n write x h'00 read ra dout auto- program 129 write x h'40 write wa din auto-erase 2 write x h'20 write x h'20 status read 2 write x h'71 write x h'71 [legend] n: number of address write cycles
rev. 4.00, 03/04, page 148 of 462 h8/38004f, h8/38002f fp-64a fp-64e socket adapter (conversion to 32-pin arrangement) pin no. pin name p71 p77 p90 p60 p61 p62 p63 p64 p65 p66 p67 p40 p41 p32 p33 p34 p35 p36 p37 p70 p42 p72 p73 p74 p75 p76 p43 vcc avcc x1 test v1 p91 p95 vss vss pb0 pb1 pb2 osc1,osc2 res (open) hn28f101 (32 pins) pin no. pin name 1 26 2 3 31 13 14 15 17 18 19 20 21 12 11 10 9 8 7 6 5 27 24 23 25 4 28 29 22 32 16 fwe a9 a16 a15 we i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 a0 a1 a2 a3 a4 a5 a6 a7 a8 oe a10 a11 a12 a13 a14 ce vcc vss 31 25 49 40 39 38 37 36 35 34 33 57 58 10 11 12 13 14 15 32 59 30 29 28 27 26 60 16 61 2 7 17 50 54 4 55 62 63 64 6, 5 8 power-on reset circuit oscillator circuit [legend] fwe: flash-write enable i/o7 to i/o0: data input/output a16 to a0: address input ce : chip enable oe : output enable we : write enable note: the oscillation frequency of the oscillator circuit should be 10 mhz. other than above figure 6.12(1) socket adapter pin correspondence diagram (h8/38004f, h8/38002f)
rev. 4.00, 03/04, page 149 of 462 h8/38104f, h8/38102f fp-64a fp-64e socket adapter (conversion to 32-pin arrangement) pin no. pin name p71 p77 p90 p60 p61 p62 p63 p64 p65 p66 p67 p40 p41 p32 p33 p34 p35 p36 p37 p70 p42 p72 p73 p74 p75 p76 p43 vcc avcc x1 test v1 p91 cvcc, p95 vss vss pb0 pb1 pb2 osc1,osc2 res (open) hn28f101 (32 pins) pin no. pin name 1 26 2 3 31 13 14 15 17 18 19 20 21 12 11 10 9 8 7 6 5 27 24 23 25 4 28 29 22 32 16 fwe a9 a16 a15 we i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 a0 a1 a2 a3 a4 a5 a6 a7 a8 oe a10 a11 a12 a13 a14 ce vcc vss 31 25 49 40 39 38 37 36 35 34 33 57 58 10 11 12 13 14 15 32 59 30 29 28 27 26 60 16 61 2 7 17 50 53, 54 4 55 62 63 64 6, 5 8 power-on reset circuit oscillator circuit [legend] fwe: flash-write enable i/o7 to i/o0: data input/output a16 to a0: address input ce : chip enable oe : output enable we : write enable note: the oscillation frequency of the oscillator circuit should be 10 mhz. other than above figure 6.12(2) socket adapter pin correspondence diagram (h8/38104f, h8/38102f)
rev. 4.00, 03/04, page 150 of 462 6.10.3 memory read mode 1. after completion of auto-program/auto-erase/status read operations, a transition is made to the command wait state. when reading memory contents, a transition to memory read mode must first be made with a command write, after which the memory contents are read. once memory read mode has been entered, consecutive reads can be performed. 2. in memory read mode, command writes can be performed in the same way as in the command wait state. 3. after powering on, memory read mode is entered. 4. tables 6.12 to 6.14 show the ac characteristics. table 6.12 ac characteristics in transition to memory read mode (conditions: v cc =3.3v0.3v,v ss =0v,ta=25c5c) item symbol min max unit test condition command write cycle t nxtc 20 ? s ce hold time t ceh 0?ns ce setup time t ces 0?ns data hold time t dh 50 ? ns data setup time t ds 50 ? ns write pulse width t wep 70 ? ns we rise time t r ?30ns we fall time t f ?30ns figure 6.13 a15 to a0 i/o7 to i/o0 command write memory read mode t ceh t ds t dh t f t r t nxtc note: data is latched on the rising edge of . t ces t wep address stable figure 6.13 timing waveforms for memory read after command write
rev. 4.00, 03/04, page 151 of 462 table 6.13 ac characteristics in transition from memory read mode to another mode (conditions: v cc =3.3v0.3v,v ss =0v,ta=25c5c) item symbol min max unit test condition command write cycle t nxtc 20 ? s ce hold time t ceh 0?ns ce setup time t ces 0?ns data hold time t dh 50 ? ns data setup time t ds 50 ? ns write pulse width t wep 70 ? ns we rise time t r ?30ns we fall time t f ?30ns figure 6.14 a15 to a0 i/o7 to i/o0 other mode command write t ceh t ds t dh t f t r t nxtc note: do not enable and at the same time. t ces t wep memory read mode address stable figure 6.14 timing waveforms in transition from memory read mode to another mode table 6.14 ac characteristics in memory read mode (conditions: v cc =3.3v0.3v,v ss =0v,ta=25c5c) item symbol min max unit test condition access time t acc ?20s ce output delay time t ce ? 150 ns oe output delay time t oe ? 150 ns output disable delay time t df ? 100 ns data output hold time t oh 5?ns figures 6.15 and 6.16
rev. 4.00, 03/04, page 152 of 462 a15 to a0 i/o7 to i/o0 t acc t oh t oh t acc address stable address stable figure 6.15 timing waveforms in ce ce ce ce and oe oe oe oe enable state read a15 to a0 i/o7 to i/o0 t ce t acc t oe t oh t oh t df t ce t acc t oe address stable address stable t df figure 6.16 timing waveforms in ce ce ce ce and oe oe oe oe clock system read 6.10.4 auto-program mode 1. when reprogramming previously programmed addresses, perform auto-erasing before auto- programming. 2. perform auto-programming once only on the same address block. it is not possible to program an address block that has already been programmed. 3. in auto-program mode, 128 bytes are programmed simultaneously. this should be carried out by executing 128 consecutive byte transfers. a 128-byte data transfer is necessary even when programming fewer than 128 bytes. in this case, h'ff data must be written to the extra addresses. 4. the lower 7 bits of the transfer address must be low. if a value other than an effective address is input, processing will switch to a memory write operation but a write error will be flagged. 5. memory address transfer is performed in the second cycle (figure 6.17). do not perform transfer after the third cycle. 6. do not perform a command write during a programming operation.
rev. 4.00, 03/04, page 153 of 462 7. perform one auto-program operation for a 128-byte block for each address. two or more additional programming operations cannot be performed on a previously programmed address block. 8. confirm normal end of auto-programming by checking i/o6. alternatively, status read mode can also be used for this purpose (i/o7 status polling uses the auto-program operation end decision pin). 9. status polling i/o6 and i/o7 pin information is retained until the next command write. as long as the next command write has not been performed, reading is possible by enabling ce and oe . 10. table 6.15 shows the ac characteristics. table 6.15 ac characteristics in auto-program mode (conditions: v cc =3.3v0.3v,v ss =0v,ta=25c5c) item symbol min max unit test condition command write cycle t nxtc 20 ? s ce hold time t ceh 0?ns ce setup time t ces 0?ns data hold time t dh 50 ? ns data setup time t ds 50 ? ns write pulse width t wep 70 ? ns status polling start time t wsts 1?ms status polling access time t spa ? 150 ns address setup time t as 0?ns address hold time t ah 60 ? ns memory write time t write 1 3000 ms we rise time t r ?30ns we fall time t f ?30ns figure 6.17
rev. 4.00, 03/04, page 154 of 462 address stable a15 to a0 i/o5 to i/o0 i/o6 i/o7 t as t ah t dh t ds tf tr t wep t wsts t write t spa t nxtc t nxtc t ceh t ces write operation end decision signal data transfer 1 to 128 bytes write normal end decision signal h'40 h'00 figure 6.17 timing waveforms in auto-program mode 6.10.5 auto-erase mode 1. auto-erase mode supports only entire memory erasing. 2. do not perform a command write during auto-erasing. 3. confirm normal end of auto-erasing by checking i/o6. alternatively, status read mode can also be used for this purpose (i/o7 status polling uses the auto-erase operation end decision pin). 4. status polling i/o6 and i/o7 pin information is retained until the next command write. as long as the next command write has not been performed, reading is possible by enabling ce and oe . 5. table 6.16 shows the ac characteristics.
rev. 4.00, 03/04, page 155 of 462 table 6.16 ac characteristics in auto-erase mode (conditions: v cc =3.3v0.3v,v ss =0v,ta=25c5c) item symbol min max unit test condition command write cycle t nxtc 20 ? s ce hold time t ceh 0?ns ce setup time t ces 0?ns data hold time t dh 50 ? ns data setup time t ds 50 ? ns write pulse width t wep 70 ? ns status polling start time t ests 1?ms status polling access time t spa ? 150 ns memory erase time t erase 100 40000 ms we rise time t r ?30ns we fall time t f ?30ns figure 6.18 a15 to a0 i/o5 to i/o0 i/o6 i/o7 t ests t erase t spa t dh t ds tf tr t wep t nxtc t nxtc t ceh t ces erase end decision signal erase normal end decision signal h'20 h'20 h'00 figure 6.18 timing waveforms in auto-erase mode
rev. 4.00, 03/04, page 156 of 462 6.10.6 status read mode 1. status read mode is provided to identify the kind of abnormal end. use this mode when an abnormal end occurs in auto-program mode or auto-erase mode. 2. the return code is retained until a command write other than command write in status read mode is executed. 3. table 6.17 shows the ac characteristics and table 6.18 shows the return codes. table 6.17 ac characteristics in status read mode (conditions: v cc =3.3v0.3v,v ss =0v,ta=25c5c) item symbol min max unit test condition read time after command write t nxtc 20 ? s ce hold time t ceh 0?ns ce setup time t ces 0?ns data hold time t dh 50 ? ns data setup time t ds 50 ? ns write pulse width t wep 70 ? ns oe output delay time t oe ? 150 ns disable delay time t df ? 100 ns ce output delay time t ce ? 150 ns we rise time t r ?30ns we fall time t f ?30ns figure 6.19 a15 to a0 i/o7 to i/o0 t dh t df t ds tf tr t wep t nxtc t nxtc tf tr t wep t ds t dh t nxtc t ceh t ceh t oe t ces t ces t ce h'71 h'71 note: i/o2 and i/o3 are undefined. figure 6.19 timing waveforms in status read mode
rev. 4.00, 03/04, page 157 of 462 table 6.18 return codes in status read mode pin name initial value description i/o7 0 1: abnormal end 0: normal end i/o6 0 1: command error 0: otherwise i/o5 0 1: programming error 0: otherwise i/o4 0 1: erasing error 0: otherwise i/o3 0 undefined i/o2 0 undefined i/o1 0 1: over counting of writing or erasing 0: otherwise i/o0 0 1: effective address error 0: otherwise 6.10.7 status polling 1. the i/o7 status polling flag indicates the operating status in auto-program/auto-erase mode. 2. the i/o6 status polling flag indicates a normal or abnormal end in auto-program/auto-erase mode. table 6.19 status polling output i/o7 i/o6 i/o0 to i/o5 status 0 0 0 during internal operation 1 0 0 abnormal end 1 1 0 normal end 01 0 ?
rev. 4.00, 03/04, page 158 of 462 6.10.8 programmer mode transition time commands cannot be accepted during the oscillation stabilization period or the programmer mode setup period. after the programmer mode setup time, a transition is made to memory read mode. table 6.20 stipulated transition times to command wait state item symbol min max unit test condition oscillation stabilization time (crystal resonator) 10 ? ms oscillation stabilization time (ceramic resonator) t osc1 5?ms programmer mode setup time t bmv 10 ? ms v cc hold time t dwn 0?ms figure 6.20 v cc auto-program mode auto-erase mode t osc1 t bmv t dwn figure 6.20 oscillation stabilization time, boot program transfer time, and power-down sequence 6.10.9 notes on memory programming 1. when performing programming using programmer mode on a chip that has been programmed/erased in on-board programming mode, auto-erasing is recommended before carrying out auto-programming. 2. the flash memory is initially in the erased state when the device is shipped by renesas. for other chips for which the erasure history is unknown, it is recommended that auto-erasing be executed to check and supplement the initialization (erase) level.
rev. 4.00, 03/04, page 159 of 462 6.11 power-down states for flash memory in user mode, the flash memory will operate in either of the following states: ? normal operating mode the flash memory can be read and written to at high speed. ? power-down operating mode the power supply circuit of flash memory can be partly halted. as a result, flash memory can be read with low power consumption. ? standby mode all flash memory circuits are halted. table 6.21 shows the correspondence between the operating modes of this lsi and the flash memory. in subactive mode, the flash memory can be set to operate in power-down mode with the pdwnd bit in flpwcr. when the flash memory returns to its normal operating state from power-down mode or standby mode, a period to stabilize operation of the power supply circuits that were stopped is needed. when the flash memory returns to its normal operating state, bits sts2 to sts0 in syscr1 must be set to provide a wait time of at least 20 s, even when the external clock is being used. table 6.21 flash memory operating states flash memory operating state lsi operating state pdwnd = 0 (initial value) pdwnd = 1 active mode normal operating mode normal operating mode subactive mode power-down mode normal operating mode sleep mode normal operating mode normal operating mode subsleep mode standby mode standby mode standby mode standby mode standby mode watch mode standby mode standby mode
rev. 4.00, 03/04, page 160 of 462
rev. 4.00, 03/04, page 161 of 462 section 7 ram this lsi has an on-chip high-speed static ram. the ram is connected to the cpu by a 16-bit data bus, enabling two-state access by the cpu to both byte data and word data. product classification ram size ram address h8/38004 1 kbyte h'fb80 to h'ff7f flash memory version h8/38002 1 kbyte h'fb80 to h'ff7f h8/38104 1 kbyte h'fb80 to h'ff7f h8/38102 1 kbyte h'fb80 to h'ff7f prom version h8/3802 1 kbyte h'fb80 to h'ff7f h8/3802 1 kbyte h'fb80 to h'ff7f h8/3801 512 bytes h'fd80 to h'ff7f h8/3800 512 bytes h'fd80 to h'ff7f h8/38004 1 kbyte h'fb80 to h'ff7f h8/38003 1 kbyte h'fb80 to h'ff7f h8/38002 1 kbyte h'fb80 to h'ff7f h8/38001 512 bytes h'fd80 to h'ff7f mask rom version h8/38000 512 bytes h'fd80 to h'ff7f h8/38104 1 kbyte h'fb80 to h'ff7f h8/38103 1 kbyte h'fb80 to h'ff7f h8/38102 1 kbyte h'fb80 to h'ff7f h8/38101 512 bytes h'fd80 to h'ff7f h8/38100 512 bytes h'fd80 to h'ff7f
rev. 4.00, 03/04, page 162 of 462 7.1 block diagram figure 7.1 shows a block diagram of the on-chip ram. internal data bus (upper 8 bits) internal data bus (lower 8 bits) h'fb80 h'fb82 h'ff7e h'fb80 h'fb82 h'ff7e h'fb81 h'fb83 h'ff7f on-chip ram even address odd address figure 7.1 block diagram of ram (h8/3802)
rev. 4.00, 03/04, page 163 of 462 section 8 i/o ports this lsi is provided with three 8-bit i/o ports, one 7-bit i/o port, one 4-bit i/o port, one 3-bit i/o port, one 1-bit i/o port, one 4-bit input-only port, one 1-bit input-only port, and one 6-bit output- only port. each port is configured by the port control register (pcr) that controls input and output, and the port data register (pdr) that stores output data. input or output can be assigned to individual bits. ports 5, 6, 7, 8, and a are also used as liquid crystal display segment and common pins, selectable in 4-bit units. see section 2.9.4, bit manipulation instructions, for information on executing bit-manipulation instructions to write data in pcr or pdr. block diagrams of each port are given in appendix b, i/o port block diagrams. table 8.1 lists the functions of each port. table 8.1 port functions port description pins other functions function switching registers p37/aevl p36/aevh p35 p34 p33 asynchronous event counter event inputs aevl, aevh pmr3 port 3 ? 7-bit i/o port ? input pull-up mos option ? large-current port * 1 p32/tmofh p31/tmofl timer f output compare output pmr3 p43/ irq0 external interrupt 0 pmr2 port 4 ? 1-bit input-only port ? 3-bit i/o port p42/txd32 p41/rxd32 p40/sck32 sci3 data output (txd32), data input (rxd32), clock input/output (sck32) scr3 smr port 5 ? 8-bit i/o port ? input pull-up mos option p57top50/ wkp7 to wkp0 / seg8 to seg1 wakeup input ( wkp7 to wkp0 ), segment output (seg8 to seg1) pmr5 lpcr port 6 ? 8-bit i/o port ? input pull-up mos option p67top60/ seg16 to seg9 segment output (seg16 to seg9) lpcr port 7 ? 8-bit i/o port p77top70/ seg24 to seg17 segment output (seg24 to seg17) lpcr port 8 ? 1-bit i/o port p80/seg25 segment output (seg25) lpcr
rev. 4.00, 03/04, page 164 of 462 port description pins other functions function switching registers p95top92 (p95, p92, p93/vref) * 3 none (lvd reference voltage external input pin) * 3 (lvdsr) * 3 ? 6-bit output-only port ? high-voltage, large-current port * 2 p91, p90/ pwm2, pwm1 10-bit pwm output pmr9 port 9 ? high-voltage, input port * 4 irqaec none port a ? 4-bit i/o port pa3 to pa0/ com4 to com1 commonoutput(com4to com1) lpcr pb3/an3/ irq1 a/d converter analog input external interrupt 1 amr pmrb port b ? 4-bit input-only port pb2/an2 a/d converter analog input amr pb1/an1/ (extu) * 5 pb0/an0/ (extd) * 5 a/d converter analog input (lvd detection voltage external input pin) * 5 amr (lvdcr) * 5 notes: 1. implemented on h8/3802 group and h8/38104 group only. 2. implemented on h8/3802 group only. standard high-voltage port on h8/38104 group and h8/38004 group. 3. implemented on h8/38104 group only. pin 94 does not function on h8/38104 group. 4. implemented on h8/3802 group only. input port on h8/38004 group and h8/38104 group. 5. implemented on h8/38104 group only.
rev. 4.00, 03/04, page 165 of 462 8.1 port 3 port 3 is an i/o port also functioning as an asynchronous event counter input pin and timer f output pin. figure 8.1 shows its pin configuration. p37/aevl p36/aevh p35 p34 p33 p32/tmofh p31/tmofl port 3 figure 8.1 port 3 pin configuration port 3 has the following registers. ? port data register 3 (pdr3) ? port control register 3 (pcr3) ? port pull-up control register 3 (pucr3) ? port mode register 3 (pmr3) ? port mode register 2 (pmr2)
rev. 4.00, 03/04, page 166 of 462 8.1.1 port data register 3 (pdr3) pdr3 is a register that stores data of port 3. bit bit name initial value r/w description 7 6 5 4 3 2 1 p37 p36 p35 p34 p33 p32 p31 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w if port 3 is read while pcr3 bits are set to 1, the values stored in pdr3 are read, regardless of the actual pin states. if port 3 is read while pcr3 bits are cleared to 0, the pin states are read. 0 ??? reserved 8.1.2 port control register 3 (pcr3) pcr3 controls whether each of the port 3 pins functions as an input pin or output pin. bit bit name initial value r/w description 7 6 5 4 3 2 1 pcr37 pcr36 pcr35 pcr34 pcr33 pcr32 pcr31 0 0 0 0 0 0 0 w w w w w w w setting a pcr3 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. the settings in pcr3 and in pdr3 are valid only when the corresponding pin is designated in pmr3 as a general i/o pin. pcr3 is a write-only register. bits 7 to 1 are always read as 1. 0 ?? w reserved thewritevalueshouldalwaysbe0.
rev. 4.00, 03/04, page 167 of 462 8.1.3 port pull-up control register 3 (pucr3) pucr3 controls whether the pull-up mos of each of the port 3 pins is on or off. bit bit name initial value r/w description 7 6 5 4 3 2 1 pucr37 pucr36 pucr35 pucr34 pucr33 pucr32 pucr31 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w when a pcr3 bit is cleared to 0, setting the corresponding pucr3 bit to 1 turns on the pull-up mos for the corresponding pin, while clearing the bit to 0 turns off the pull-up mos. 0 ?? w reserved thewritevalueshouldalwaysbe0.
rev. 4.00, 03/04, page 168 of 462 8.1.4 port mode register 3 (pmr3) pmr3 controls the selection of pin functions for port 3 pins. bit bit name initial value r/w description 7 aevl 0 r/w p37/aevl pin function switch this bit selects whether pin p37/aevl is used as p37 or as aevl. 0: p37 i/o pin 1: aevl input pin 6 aevh 0 r/w p36/aevh pin function switch this bit selects whether pin p36/aevh is used as p36 or as aevh. 0: p36 i/o pin 1: aevh input pin 5to3 ?? w reserved thewritevalueshouldalwaysbe0. 2tmofh0r/w p32/tmofh pin function switch this bit selects whether pin p32/tmofh is used as p32 or as tmofh. 0: p32 i/o pin 1: tmofh output pin 1tmofl0r/w p31/tmofl pin function switch this bit selects whether pin p31/tmofl is used as p31 or as tmofl. 0: p31 i/o pin 1: tmofl output pin 0 ?? w reserved thewritevalueshouldalwaysbe0.
rev. 4.00, 03/04, page 169 of 462 8.1.5 port mode register 2 (pmr2) pmr2 controls the pmos on/off state for the p35 pin, selects a pin function for the p43/ irq0 pin, and selects a clock of the watchdog timer. bit bit name initial value r/w description 7, 6 ? all 1 ? reserved these bits are always read as 1 and cannot be modified. 5 pof1 0 r/w p35 pin pmos control this bit controls the on/off state of the pmos of the p35 pin output buffer. 0: cmos output 1: nmos open-drain output 4, 3 ? all 1 ? reserved these bits are always read as 1 and cannot be modified. 2wdcks0r/wwatchdogtimersourceclockselect this bit selects the input clock for the watchdog timer. note that this bit is implemented differently on the h8/38004 group and on h8/38104 group. h8/38004 group: 0: /8,192 1: w/32 h8/38104 group: 0: clock specified by timer mode register w (tmw) 1: w/32 note: this bit is reserved and only 0 can be written in the h8/3802 group. 1 ?? w reserved thewritevalueshouldalwaysbe0. 0 irq0 0 r/w p43/ irq0 pin function switch this bit selects whether pin p43/ irq0 is used as p43 or as irq0 . 0: p43 input pin 1: irq0 input pin note: * see section 9.5, watchdog timer, for details.
rev. 4.00, 03/04, page 170 of 462 8.1.6 pin functions the port 3 pin functions are shown below. ? p37/aevl pin the pin function depends on the combination of bit aevl in pmr3 and bit pcr37 in pcr3. aevl 0 1 pcr37 0 1 * pin function p37 input pin p37 output pin aevl input pin [legend] * : don't care. ? p36/aevh pin the pin function depends on the combination of bit aevh in pmr3 and bit pcr36 in pcr3. aevh 0 1 pcr36 0 1 * pin function p36 input pin p36 output pin aevh input pin [legend] * : don't care. ? p35top33pins the pin function depends on the corresponding bit in pcr3. (n = 5 to 3) pcr3n 0 1 pin function p3n input pin p3n output pin ? p32/tmofh pin the pin function depends on the combination of bit tmofh in pmr3 and bit pcr32 in pcr3. tmofh 0 1 pcr32 0 1 * pin function p32 input pin p32 output pin tmofh output pin [legend] * : don't care.
rev. 4.00, 03/04, page 171 of 462 ? p31/tmofl pin the pin function depends on the combination of bit tmofl in pmr3 and bit pcr31 in pcr3. tmofl 0 1 pcr31 0 1 * pin function p31 input pin p31 output pin tmofl output pin [legend] * : don't care. 8.1.7 input pull-up mos port 3 has an on-chip input pull-up mos function that can be controlled by software. when the pcr3 bit is cleared to 0, setting the corresponding pucr3 bit to 1 turns on the input pull-up mos for that pin. the input pull-up mos function is in the off state after a reset. (n = 7 to 1) pcr3n 0 1 pucr3n 0 1 * input pull-up mos off on off [legend] * : don't care.
rev. 4.00, 03/04, page 172 of 462 8.2 port 4 port 4 is an i/o port also functioning as an interrupt input pin and sci i/o pin. figure 8.2 shows its pin configuration. p43/ p42/txd32 p41/rxd32 p40/sck32 port 4 figure 8.2 port 4 pin configuration port 4 has the following registers. ? port data register 4 (pdr4) ? port control register 4 (pcr4) ? serial port control register (spcr) 8.2.1 port data register 4 (pdr4) pdr4 is a register that stores data of port 4. bit bit name initial value r/w description 7to4 ? 1 ? reserved these bits are always read as 1. 3 2 1 0 p43 p42 p41 p40 1 0 0 0 r r/w r/w r/w if port 4 is read while pcr4 bits are set to 1, the values stored in pdr4 are read, regardless of the actual pin states. if port 4 is read while pcr4 bits are cleared to 0, the pin states are read.
rev. 4.00, 03/04, page 173 of 462 8.2.2 port control register 4 (pcr4) pcr4 controls whether each of the port 4 pins functions as an input pin or output pin. bit bit name initial value r/w description 7to3 ? all 1 ? reserved these bits are always read as 1. 2 1 0 pcr42 pcr41 pcr40 0 0 0 w w w setting a pcr4 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. the settings in pcr4 and in pdr4 are valid only when the corresponding pin is designated in scr3 and scr2 as a general i/o pin. pcr4 is a write-only register. bits 2 to 0 are always read as 1. 8.2.3 serial port control register (spcr) spcr performs input/output data inversion switching of the rxd32 and txd32 pins. figure 8.3 shows the configuration. scinv2 p41/rxd32 p42/txd32 rxd32 txd32 scinv3 figure 8.3 input/output data inversion function
rev. 4.00, 03/04, page 174 of 462 bit bit name initial value r/w description 7, 6 ? all 1 ? reserved these bits are always read as 1 and cannot be modified. 5 spc32 0 r/w p42/txd32 pin function switch this bit selects whether pin p42/txd32 is used as p42 or as txd32. 0: p42 i/o pin 1: txd32 output pin * note: * set the te bit in scr3 after setting this bit to 1. 4 ?? w reserved thewritevalueshouldalwaysbe0. 3 scinv3 0 r/w txd32 pin output data inversion switch this bit specifies whether or not txd32 pin output data is to be inverted. 0: txd32 output data is not inverted 1: txd32 output data is inverted 2 scinv2 0 r/w rxd32 pin input data inversion switch this bit specifies whether or not rxd32 pin input data is to be inverted. 0: rxd32 input data is not inverted 1: rxd32 input data is inverted 1, 0 ?? w reserved thewritevalueshouldalwaysbe0. note: when the serial port control register is modified, the data being input or output up to that point is inverted immediately after the modification, and an invalid data change is input or output. when modifying the serial port control register, modification must be made in a state in which data changes are invalidated.
rev. 4.00, 03/04, page 175 of 462 8.2.4 pin functions the port 4 pin functions are shown below. ? p43/ irq0 pin the pin function depends on the irq0 bit in pmr2. irq0 0 1 pin function p43 input pin irq0 input pin ? p42/txd32 pin the pin function depends on the combination of bit te in scr3, bit spc32 in spcr, and bit pcr42 in pcr4. spc32 0 1 te 0 1 pcr42 0 1 * pin function p42 input pin p42 output pin txd32 output pin [legend] * : don't care. ? p41/rxd32 pin the pin function depends on the combination of bit re in scr3 and bit pcr41 in pcr4. re 0 1 pcr41 0 1 * pin function p41 input pin p41 output pin rxd32 input pin [legend] * : don't care.
rev. 4.00, 03/04, page 176 of 462 ? p40/sck32 pin the pin function depends on the combination of bits cke1 and cke0 in scr3, bit com in smr, and bit pcr40 in pcr4. cke1 0 1 cke0 0 1 * com 0 1 ** pcr40 0 1 ** pin function p40 input pin p40 output pin sck32 output pin sck32 input pin [legend] * : don't care. 8.3 port 5 port 5 is an i/o port also functioning as a wakeup interrupt request input pin and lcd segment output pin. figure 8.4 shows its pin configuration. p57/ /seg8 p56/ /seg7 p55/ /seg6 p54/ /seg5 p53/ /seg4 p52/ /seg3 p51/ /seg2 p50/ /seg1 port 5 figure 8.4 port 5 pin configuration port 5 has the following registers. ? port data register 5 (pdr5) ? port control register 5 (pcr5) ? port pull-up control register 5 (pucr5) ? port mode register 5 (pmr5)
rev. 4.00, 03/04, page 177 of 462 8.3.1 port data register 5 (pdr5) pdr5 is a register that stores data of port 5. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 p57 p56 p55 p54 p53 p52 p51 p50 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w if port 5 is read while pcr5 bits are set to 1, the values stored in pdr5 are read, regardless of the actual pin states. if port 5 is read while pcr5 bits are cleared to 0, the pin states are read. 8.3.2 port control register 5 (pcr5) pcr5 controls whether each of the port 5 pins functions as an input pin or output pin. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 pcr57 pcr56 pcr55 pcr54 pcr53 pcr52 pcr51 pcr50 0 0 0 0 0 0 0 0 w w w w w w w w setting a pcr5 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. the settings in pcr5 and in pdr5 are valid only when the corresponding pin is designated by pmr5 and the sgs3 to sgs0 bits in lpcr as a general i/o pin. pcr5 is a write-only register. bits 7 to 0 are always read as 1.
rev. 4.00, 03/04, page 178 of 462 8.3.3 port pull-up control register 5 (pucr5) pucr5 controls whether the pull-up mos of each of the port 5 pins is on or off. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 pucr57 pucr56 pucr55 pucr54 pucr53 pucr52 pucr51 pucr50 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w when a pcr5 bit is cleared to 0, setting the corresponding pucr5 bit to 1 turns on the pull-up mos for the corresponding pin, while clearing the bit to 0 turns off the pull-up mos. 8.3.4 port mode register 5 (pmr5) pmr5 controls the selection of pin functions for port 5 pins. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 wkp7 wkp6 wkp5 wkp4 wkp3 wkp2 wkp1 wkp0 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w p5n/ wkpn /segn + 1 pin function switch when pin p5n/ wkpn /segn + 1 is not used as segn + 1, these bits select whether the pin is used as p5n or wkpn . 0: p5n i/o pin 1: wkpn input pin (n = 7 to 0) note: for use as segn+1, see section 13.3.1, lcd port control register (lpcr).
rev. 4.00, 03/04, page 179 of 462 8.3.5 pin functions the port 5 pin functions are shown below. ? p57/ wkp7 /seg8top54/ wkp4 /seg5 pins the pin function depends on the combination of bit wkpn in pmr5, bit pcr5n in pcr5, and bits sgs3 to sgs0 in lpcr. (n = 7 to 4) sgs3 to sgs0 other than b 0010, b 0011, b 0100, b 0101, b 0110, b 0111, b 1000, b 1001 b 0010, b 0011, b 0100, b 0101, b 0110, b 0111, b 1000, b 1001 wkpn 0 1 * pcr5n 0 1 ** pin function p5n input pin p5n output pin wkpn input pin segn+1 output pin [legend] * : don't care. ? p53/ wkp3 /seg4top50/ wkp0 /seg1 pins the pin function depends on the combination of bit wkpm in pmr5, bit pcr5m in pcr5, and bits sgs3 to sgs0 in lpcr. (m = 3 to 0) sgs3 to sgs0 other than b 0001, b 0010, b 0011, b 0100, b 0101, b 0110, b 0111, b 1000 b 0001, b 0010, b 0011, b 0100, b 0101, b 0110, b 0111, b 1000 wkpm 0 1 * pcr5m 0 1 ** pin function p5m input pin p5m output pin wkpm input pin segm+1 output pin [legend] * : don't care.
rev. 4.00, 03/04, page 180 of 462 8.3.6 input pull-up mos port 5 has an on-chip input pull-up mos function that can be controlled by software. when the pcr5 bit is cleared to 0, setting the corresponding pucr5 bit to 1 turns on the input pull-up mos for that pin. the input pull-up mos function is in the off state after a reset. (n = 7 to 0) pcr5n 0 1 pucr5n 0 1 * input pull-up mos off on off [legend] * : don't care. 8.4 port 6 port 6 is an i/o port also functioning as an lcd segment output pin. figure 8.5 shows its pin configuration. p67/seg16 p66/seg15 p65/seg14 p64/seg13 p63/seg12 p62/seg11 p61/seg10 p60/seg9 port 6 figure 8.5 port 6 pin configuration port 6 has the following registers. ? port data register 6 (pdr6) ? port control register 6 (pcr6) ? port pull-up control register 6 (pucr6)
rev. 4.00, 03/04, page 181 of 462 8.4.1 port data register 6 (pdr6) pdr6 is a register that stores data of port 6. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 p67 p66 p65 p64 p63 p62 p61 p60 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w if port 6 is read while pcr6 bits are set to 1, the values stored in pdr6 are read, regardless of the actual pin states. if port 6 is read while pcr6 bits are cleared to 0, the pin states are read. 8.4.2 port control register 6 (pcr6) pcr6 controls whether each of the port 6 pins functions as an input pin or output pin. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 pcr67 pcr66 pcr65 pcr64 pcr63 pcr62 pcr61 pcr60 0 0 0 0 0 0 0 0 w w w w w w w w setting a pcr6 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. the settings in pcr6 and in pdr6 are valid only when the corresponding pin is designated by the sgs3 to sgs0 bits in lpcr as a general i/o pin. pcr6 is a write-only register. bits 7 to 0 are always read as 1.
rev. 4.00, 03/04, page 182 of 462 8.4.3 port pull-up control register 6 (pucr6) pucr6 controls whether the pull-up mos of each of the port 6 pins is on or off. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 pucr67 pucr66 pucr65 pucr64 pucr63 pucr62 pucr61 pucr60 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w when a pcr6 bit is cleared to 0, setting the corresponding pucr6 bit to 1 turns on the pull-up mos for the corresponding pin, while clearing the bit to 0 turns off the pull-up mos. 8.4.4 pin functions the port 6 pin functions are shown below. ? p67/seg16 to p64/seg13 pins the pin function depends on the combination of bit pcr6n in pcr6 and bits sgs3 to sgs0 in lpcr. (n = 7 to 4) sgs3 to sgs0 other than b 0100, b 0101, b 0110, b 0111, b 1000, b 1001, b 1010, b 1011 b 0100, b 0101, b 0110, b 0111, b 1000, b 1001, b 1010, b 1011 pcr6n 0 1 * pin function p6n input pin p6n output pin segn+9 output pin [legend] * : don't care.
rev. 4.00, 03/04, page 183 of 462 ? p63/seg12 to p60/seg9 pins the pin function depends on the combination of bit pcr6m in pcr6 and bits sgs3 to sgs0 in lpcr. (m = 3 to 0) sgs3 to sgs0 other than b 0011, b 0100, b 0101, b 0110, b 0111, b 1000, b 1001, b 1010 b 0011, b 0100, b 0101, b 0110, b 0111, b 1000, b 1001, b 1010 pcr6m 0 1 * pin function p6m input pin p6m output pin segm+9 output pin [legend] * : don't care. 8.4.5 input pull-up mos port 6 has an on-chip input pull-up mos function that can be controlled by software. when the pcr6 bit is cleared to 0, setting the corresponding pucr6 bit to 1 turns on the input pull-up mos for that pin. the input pull-up mos function is in the off state after a reset. (n = 7 to 0) pcr6n 0 1 pucr6n 0 1 * input pull-up mos off on off [legend] * : don't care.
rev. 4.00, 03/04, page 184 of 462 8.5 port 7 port 7 is an i/o port also functioning as an lcd segment output pin. figure 8.6 shows its pin configuration. p77/seg24 p76/seg23 p75/seg22 p74/seg21 p73/seg20 p72/seg19 p71/seg18 p70/seg17 port 7 figure 8.6 port 7 pin configuration port 7 has the following registers. ? port data register 7 (pdr7) ? port control register 7 (pcr7) 8.5.1 port data register 7 (pdr7) pdr7 is a register that stores data of port 7. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 p77 p76 p75 p74 p73 p72 p71 p70 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w if port 7 is read while pcr7 bits are set to 1, the values stored in pdr7 are read, regardless of the actual pin states. if port 7 is read while pcr7 bits are cleared to 0, the pin states are read.
rev. 4.00, 03/04, page 185 of 462 8.5.2 port control register 7 (pcr7) pcr7 controls whether each of the port 7 pins functions as an input pin or output pin. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 pcr77 pcr76 pcr75 pcr74 pcr73 pcr72 pcr71 pcr70 0 0 0 0 0 0 0 0 w w w w w w w w setting a pcr7 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. the settings in pcr7 and in pdr7 are valid only when the corresponding pin is designated by the sgs3 to sgs0 bits in lpcr as a general i/o pin. pcr7 is a write-only register. bits 7 to 0 are always read as 1. 8.5.3 pin functions the port 7 pin functions are shown below. ? p77/seg24 to p74/seg21 pins the pin function depends on the combination of bit pcr7n in pcr7 and bits sgs3 to sgs0 in lpcr. (n = 7 to 4) sgs3 to sgs0 other than b 0110, b 0111, b 1000, b 1001, b 1010, b 1011, b 1100, b 1101 b 0110, b 0111, b 1000, b 1001, b 1010, b 1011, b 1100, b 1101 pcr7n 0 1 * pin function p7n input pin p7n output pin segn+17 output pin [legend] * : don't care.
rev. 4.00, 03/04, page 186 of 462 ? p73/seg20 to p70/seg17 pins the pin function depends on the combination of bit pcr7m in pcr7 and bits sgs3 to sgs0 in lpcr. (m = 3 to 0) sgs3 to sgs0 other than b 0101, b 0110, b 0111, b 1000, b 1001, b 1010, b 1011, b 1100 b 0101, b 0110, b 0111, b 1000, b 1001, b 1010, b 1011, b 1100 pcr7m 0 1 * pin function p7m input pin p7m output pin segm+17 output pin [legend] * : don't care. 8.6 port 8 port 8 is an i/o port also functioning as an lcd segment output pin. figure 8.7 shows its pin configuration. p80/seg25 port 8 figure 8.7 port 8 pin configuration port 8 has the following registers. ? port data register 8 (pdr8) ? port control register 8 (pcr8)
rev. 4.00, 03/04, page 187 of 462 8.6.1 port data register 8 (pdr8) pdr8 is a register that stores data of port 8. bit bit name initial value r/w description 7to1 ??? reserved 0 p80 0 r/w if port 8 is read while pcr8 bits are set to 1, the values stored in pdr8 are read, regardless of the actual pin states. if port 8 is read while pcr8 bits are cleared to 0, the pin states are read. 8.6.2 port control register 8 (pcr8) pcr8 controls whether each of the port 8 pins functions as an input pin or output pin. bit bit name initial value r/w description 7to1 ?? w reserved thewritevalueshouldalwaysbe0. 0 pcr80 0 w setting a pcr8 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. the settings in pcr8 and in pdr8 are valid only when the corresponding pin is designated by the sgs3 to sgs0 bits in lpcr as a general i/o pin. pcr8 is a write-only register. 8.6.3 pin functions the port 8 pin functions are shown below. ? p80/seg25 pin the pin function depends on the combination of bit pcr80 in pcr8 and bits sgs3 to sgs0 in lpcr. sgs3 to sgs0 other than b 0111, b 1000, b 1001, b 1010, b 1011, b 1100, b 1101, b 1110 b 0111, b 1000, b 1001, b 1010, b 1011, b 1100, b 1101, b 1110 pcr80 0 1 * pin function p80 input pin p80 output pin seg25 output pin [legend] * : don't care.
rev. 4.00, 03/04, page 188 of 462 8.7 port 9 port 9 is an output-only port also functioning as a pwm output pin. figure 8.8 shows its pin configuration. p95 p94 * 1 p93/vref * 2 p92 p91/pwm2 p90/pwm1 port 9 notes: 1. there is no pin 94, and its function is not implemented, on the h8/38104 group. 2. the vref pin is implemented on the h8/38104 group only. figure 8.8 port 9 pin configuration port 9 has the following registers. ? port data register 9 (pdr9) ? port mode register 9 (pmr9) 8.7.1 port data register 9 (pdr9) pdr9 is a register that stores data of port 9. bit bit name initial value r/w description 7, 6 ? all 1 ? reserved the initial value should not be changed. 5 4 3 2 1 0 p95 p94 * p93 p92 p91 p90 1 1 1 1 1 1 r/w r/w r/w r/w r/w r/w if pdr9 is read, the values stored in pdr9 are read. note: * there is no pin 94, and its function is not implemented, on the h8/38104 group. however, the register is read/write enabled.
rev. 4.00, 03/04, page 189 of 462 8.7.2 port mode register 9 (pmr9) pmr9 controls the selection of the p90 and p91 pin functions. bit bit name initial value r/w description 7to4 ? all 1 ? reserved the initial value should not be changed. 3 pioff 0 r/w p92top90step-upcircuitcontrol this bit turns on and off the p92 to p90 step-up circuit. 0: step-up circuit of large-current port is turned on 1: step-up circuit of large-current port is turned off note: this is a readable/writable reserved bit in the h8/38004 group and h8/38104 group. 2 ?? w reserved thewritevalueshouldalwaysbe0. 1 0 pwm2 pwm1 0 0 r/w r/w p9n/pwmn + 1pinfunctionswitch these bits select whether pin p9n/pwmn + 1isusedas p9n or as pwmn + 1. (n = 1, 0) 0: p9n output pin 1: pwmn + 1 output pin note: when turning the step-up circuit on or off, the register must be rewritten only when the buffer nmos is off (port data is 1). when turning the step-up circuit on, first clear pioff to 0, then wait for the elapse of 30 system clock before turning the buffer nmos on (clearing port data to 0). without the elapse of the 30 system clock interval the step-up circuit will not start up, and it will not be possible for a large current to flow, making operation unstable. 8.7.3 pin functions the port 9 pin functions are shown below. ? p91/pwmn+1 to p90/pwmn+1 pins (n = 1, 0) pmr9n 0 1 pin function p9n output pin pwmn+1 output pin
rev. 4.00, 03/04, page 190 of 462 ? p93/vref as shown below, switching is performed based on the setting of vcss in lvdsr. note that this function is implemented on the h8/38104 group only. the v ref pin is the input pin for the lvd?s external reference voltage. vcss1 0 1 pin function p93 output pin vref input pin 8.8 port a port a is an i/o port also functioning as an lcd common output pin. figure 8.9 shows its pin configuration. pa3/com4 pa2/com3 pa1/com2 pa0/com1 port a figure 8.9 port a pin configuration port a has the following registers. ? port data register a (pdra) ? port control register a (pcra) 8.8.1 port data register a (pdra) pdra is a register that stores data of port a. bit bit name initial value r/w description 7to4 ? all 1 ? reserved the initial value should not be changed. 3 2 1 0 pa3 pa2 pa1 pa0 0 0 0 0 r/w r/w r/w r/w if port a is read while pcra bits are set to 1, the values stored in pdra are read, regardless of the actual pin states. if port a is read while pcra bits are cleared to 0, the pin states are read.
rev. 4.00, 03/04, page 191 of 462 8.8.2 port control register a (pcra) pcra controls whether each of the port a pins functions as an input pin or output pin. bit bit name initial value r/w description 7to4 ? all 1 ? reserved the initial value should not be changed. 3 2 1 0 pcra3 pcra2 pcra1 pcra0 0 0 0 0 w w w w setting a pcra bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. the settings in pcra and in pdra are valid only when the corresponding pin is designated in lpcr as a general i/o pin. pcra is a write-only register. bits 3 to 0 are always read as 1. 8.8.3 pin functions the port a pin functions are shown below. ? pa3/com4 pin the pin function depends on the combination of bit pcra3 in pcra and bits sgs3 to sgs0 in lpcr. sgs3 to sgs0 b 0000 b 0000 other than b 0000 pcra3 0 1 * pin function pa3 input pin pa3 output pin com4 output pin [legend] * : don't care. ? pa2/com3 pin the pin function depends on the combination of bit pcra2 in pcra and bits sgs3 to sgs0 in lpcr. sgs3 to sgs0 b 0000 b 0000 other than b 0000 pcra2 0 1 * pin function pa2 input pin pa2 output pin com3 output pin [legend] * : don't care.
rev. 4.00, 03/04, page 192 of 462 ? pa1/com2 pin the pin function depends on the combination of bit pcra1 in pcra and bits sgs3 to sgs0 in lpcr. sgs3 to sgs0 b 0000 b 0000 other than b 0000 pcra1 0 1 * pin function pa1 input pin pa1 output pin com2 output pin [legend] * : don't care. ? pa0/com1 pin the pin function depends on the combination of bit pcra0 in pcra and bits sgs3 to sgs0 in lpcr. sgs3 to sgs0 b 0000 b 0000 other than b 0000 pcra0 0 1 * pin function pa0 input pin pa0 output pin com1 output pin [legend] * : don't care. 8.9 port b port b is an input-only port also functioning as an analog input pin and interrupt input pin. figure 8.10 shows its pin configuration. pb3/an3/ irq1 pb2/an2 pb1/an1/extu * pb0/an0/extd * port b note: * the extu and extd pins are implemented on the h8/38104 group only. figure 8.10 port b pin configuration port b has the following registers. ? port data register b (pdrb) ? port mode register b (pmrb)
rev. 4.00, 03/04, page 193 of 462 8.9.1 port data register b (pdrb) pdrb is a register that stores data of port b. bit bit name initial value r/w description 7to4 ? undefined ? reserved 3 2 1 0 pb3 pb2 pb1 pb0 undefined r r r r reading pdrb always gives the pin states. however, if a port b pin is selected as an analog input channel for the a/d converter by bits ch3 to ch0 in amr, that pin reads 0 regardless of the input voltage. 8.9.2 port mode register b (pmrb) pmrb controls the selection of the pb3 pin functions. bit bit name initial value r/w description 7to4 ? all 1 ? reserved these bits are always read as 1 and cannot be modified. 3 irq1 0 r/w pb3/an3/ irq1 pin function switch this bit selects whether pin pb3/an3/ irq1 is used as pb3/an3 or as irq1 . 0: pb3/an3 input pin 1: irq1 input pin 2to0 ? all 1 ? reserved these bits are always read as 1 and cannot be modified. note: rising or falling edge sensing can be selected for the irq1 pin.
rev. 4.00, 03/04, page 194 of 462 8.9.3 pin functions the port b pin functions are shown below. ? pb3/an3/ irq1 pin the pin function depends on the combination of bits ch3 to ch0 in amr and bit irq1 in pmrb. irq1 0 1 ch3 to ch0 other than b 0111 b 0111 * pin function pb3 input pin an3 input pin irq1 input pin [legend] * : don't care. ? pb2/an2 pin the pin function depends on bits ch3 to ch0 in amr. ch3 to ch0 other than b 0110 b 0110 pin function pb2 input pin an2 input pin ? pb1/an1/extu pin switching is accomplished by combining ch3 to ch0 in amr and vintusel in lvdcr as shown below. note that the extu pin and vintusel are implemented on the h8/38104 group only. vintusel 0 1 ch3 to ch0 other than b 0101 b'0101 * pin function pb1 input pin an1 input pin extu input pin [legend] * : don't care ? pb0/an0/extd pin switching is accomplished by combining ch3 to ch0 in amr and vintdsel in lvdcr as shown below. note that the extd pin and vintdsel are implemented on the h8/38104 group only. vintdsel 0 1 ch3 to ch0 other than b 0100 b'0100 * pin function pb0 input pin an0 input pin extd input pin [legend] * : don't care
rev. 4.00, 03/04, page 195 of 462 8.10 usage notes 8.10.1 how to handle unused pin if an i/o pin not used by the user system is floating, pull it up or down. ? if an unused pin is an input pin, handle it in one of the following ways: ? pull it up to vcc with an on-chip pull-up mos. ? pull it up to vcc with an external resistor of approximately 100 k ? . ? pull it down to vss with an external resistor of approximately 100 k ? . ? for a pin also used by the a/d converter, pull it up to avcc. ? if an unused pin is an output pin, handle it in one of the following ways: ? set the output of the unused pin to high and pull it up to vcc with an on-chip pull-up mos. ? set the output of the unused pin to high and pull it up to vcc with an external resistor of approximately 100 k ? . ? set the output of the unused pin to low and pull it down to gnd with an external resistor of approximately 100 k ? .
rev. 4.00, 03/04, page 196 of 462
rev. 4.00, 03/04, page 197 of 462 section 9 timers 9.1 overview the h8/3802 group provides three timers: timer a, timer f, and asynchronous event counter. the h8/38004 group and h8/38104 group provide four timers: timer a, timer f, asynchronous event counter, and watchdog timer. the functions of these timers are summarized in table 9.1.
rev. 4.00, 03/04, page 198 of 462 table 9.1 timer functions name functions internal clock event input pin waveform output pin remarks ? 8-bit timer /8 to /8192 ? interval function (8 choices) timer a ? clock time base w /128 (choice of 4 overflow periods) ?? timer f ? 16-bit timer ? also usable as two independent 8-bit timers. ? output compare output function /4 to /32, w /4 (4 choices) ?tmofl tmofh asynchro- nous event counter ? 16-bit counter ? also usable as two independent 8-bit counters ? counts events asynchronous to and w ? can count asynchronous events (rising/falling/both edges) independ- ently of the mcu's internal clock /2 to /8 (3 choices) aevl aevh irqaec ? watchdog timer * /8192, w /32 ?? h8/38004 group ? generates a reset signal by overflow of 8-bit counter /64 to /8192 w/32 on-chip oscillator h8/38104 group note: * the watchdog timer functions differently on the h8/38004 and h8/38104 group. see section 9.5, watchdog timer, for details.
rev. 4.00, 03/04, page 199 of 462 9.2 timer a the timer a is an 8-bit timer with interval timing and realtime clock time-base functions. the clock time-base function is available when a 32.768khz crystal oscillator is connected. figure 9.1 shows a block diagram of the timer a. 9.2.1 features ? the timer a can be used as an interval timer or a clock time base. ? an interrupt is requested when the counter overflows. ? use of module standby mode enables this module to be placed in standby mode independently when not used. (for details, refer to section 5.4, module standby function.) interval timer ? choice of eight internal clock sources ( /8192, /4096, /2048, /512, /256, /128, /32, and 8) clock time base ? choice of four overflow periods (1 s, 0.5 s, 0.25 s, and 31.25 ms) when timer a is used as a clock time base (using a 32.768 khz crystal oscillator).
rev. 4.00, 03/04, page 200 of 462 w /8192, /4096, /2048, /512, /256, /128, /32, /8 w /128 w /4 1/4 psw pss tma tca irrta 8 * 64 * 128 * 256 * [legend] tma: timer mode register a tca: timer counter a irrta: timer a overflow interrupt request flag psw: prescaler w pss: prescaler s note: * can be selected only when the prescaler w output ( w /128) is used as the tca input clock. internal data bus figure 9.1 block diagram of timer a 9.2.2 register descriptions the timer a has the following registers. ? timer mode register a (tma) ? timer counter a (tca) timermoderegistera(tma): tma selects the operating mode, the divided clock output, and the input clock. bit bit name initial value r/w description 7 6 5 ? ? ? ? ? ? w w w reserved thewritevalueshouldalwaysbe0. 4 ? 1 ? reserved this bit is always read as 1.
rev. 4.00, 03/04, page 201 of 462 bit bit name initial value r/w description 3 tma3 0 r/w internal clock select 3 selects the operating mode of the timer a. 0: functions as an interval timer to count the outputs of prescaler s. 1: functions as a clock-time base to count the outputs of prescaler w. 2 1 0 tma2 tma1 tma0 0 0 0 r/w r/w r/w internal clock select 2 to 0 select the clock input to tca when tma3 = 0. 000: /8192 001: /4096 010: /2048 011: /512 100: /256 101: /128 110: /32 111: /8 these bits select the overflow period when tma3 = 1 (when a 32.768 khz crystal oscillator is used as w). 000: 1 s 001: 0.5 s 010: 0.25 s 011: 0.03125 s 1xx: both psw and tca are reset [legend] x: don't care. timer counter a (tca): tca is an 8-bit readable up-counter, which is incremented by internal clock input. the clock source for input to this counter is selected by bits tma3 to tma0 in tma. tca values can be read by the cpu in active mode, but cannot be read in subactive mode. when tca overflows, the irrta bit in the interrupt request register 1 (irr1) is set to 1. tca is cleared by setting bits tma3 and tma2 in tma to b'11. tca is initialized to h'00.
rev. 4.00, 03/04, page 202 of 462 9.2.3 operation interval timer operation: when bit tma3 in tma is cleared to 0, the timer a functions as an 8-bit interval timer. upon reset, tca is cleared to h'00 and bit tma3 is cleared to 0, so up-counting of the timer a resume immediately as an interval timer. the clock input to timer a is selected by bits tma2 to tma0 in tma; any of eight internal clock signals output by prescaler s can be selected. after the count value in tca reaches h'ff, the next clock signal input causes timer a to overflow, setting bit irrta to 1 in interrupt flag register 1 (irr1). if ienta = 1 in the interrupt enable register 1 (ienr1), a cpu interrupt is requested. at overflow, tca returns to h'00 and starts counting up again. in this mode the timer a functions as an interval timer that generates an overflow output at intervals of 256 input clock pulses. clock time base operation: when bit tma3 in tma is set to 1, the timer a functions as a clock-timer base by counting clock signals output by prescaler w. when a clock signal is input after the tca counter value has become h'ff, the timer a overflows and irrta in irr1 is set to 1. at that time, an interrupt request is generated to the cpu if ienta in the interrupt enable register 1 (ienr1) is 1. the overflow period of timer a is set by bits tma1 and tma0 in tma. a choice of four periods is available. in clock time base operation (tma3 = 1), setting bit tma2 to 1 clears both tca and prescaler w to h'00. 9.2.4 timer a operating states table 9.2 summarizes the timer a operating states. table 9.2 timer a operating states operating mode reset active sleep watch sub-active sub-sleep standby module standby interval reset functions functions halted halted halted halted halted tca clock time base reset functions * functions * functions functions functions halted halted tma reset functions retained retained functions retained retained retained note: * when the clock time base function is selected as the internal clock of tca in active mode or sleep mode, the internal clock is not synchronous with the system clock, so it is synchronized by a synchronizing circuit. this may result in a maximum error of 1/ (s) in the count cycle.
rev. 4.00, 03/04, page 203 of 462 9.3 timer f the timer f has a 16-bit timer having an output compare function. the timer f also provides for counter resetting, interrupt request generation, toggle output, etc., using compare match signals. thus, it can be applied to various systems. the timer f can also be used as two independent 8-bit timers (timer fh and timer fl). figure 9.2 shows a block diagram of the timer f. 9.3.1 features ? choice of four internal clock sources ( /32, /16, /4, and w /4) ? toggle output function toggleoutputisperformedtothetmofhpin(tmoflpin)usingasinglecomparematch signal. the initial value of toggle output can be set. ? counter resetting by a compare match signal ? two interrupt sources: one compare match, one overflow ? choice of 16-bit or 8-bit mode by settings of bits cksh2 to cksh0 in tcrf ? can operate in watch mode, subactive mode, and subsleep mode when w /4 is selected as an internal clock, the timer f can operate in watch mode, subactive mode, and subsleep mode. ? use of module standby mode enables this module to be placed in standby mode independently when not used. (for details, refer to section 5.4, module standby function.)
rev. 4.00, 03/04, page 204 of 462 pss toggle circuit toggle circuit w /4 tmofl tmofh tcrf tcfl ocrfl tcfh ocrfh tcsrf comparator comparator match internal data bus irrtfh irrtfl [legend] tcrf tcsrf tcfh tcfl ocrfh ocrfl irrtfh irrtfl pss : timer control register f : timer control status register f : 8-bit timer counter fh : 8-bit timer counter fl : output compare register fh : output compare register fl : timer fh interrupt request flag : timer fl interrupt request flag : prescaler s figure 9.2 block diagram of timer f 9.3.2 input/output pins table 9.3 shows the pin configuration of the timer f. table 9.3 pin configuration name abbreviation i/o function timer fh output tmofh output timer fh toggle output pin timer fl output tmofl output timer fl toggle output pin
rev. 4.00, 03/04, page 205 of 462 9.3.3 register descriptions the timer f has the following registers. ? timer counters fh and fl (tcfh,tcfl) ? output compare registers fh and fl (ocrfh, ocrfl) ? timer control register f (tcrf) ? timer control status register f (tcsrf) timer counters fh and fl (tcfh, tcfl): tcf is a 16-bit read/write up-counter configured by cascaded connection of 8-bit timer counters tcfh and tcfl. in addition to the use of tcf as a 16-bit counter with tcfh as the upper 8 bits and tcfl as the lower 8 bits, tcfh and tcfl can also be used as independent 8-bit counters. tcfh and tcfl can be read and written by the cpu, but when they are used in 16-bit mode, data transfer to and from the cpu is performed via a temporary register (temp). for details of temp, see section 9.3.4, cpu interface. tcfh and tcfl are initialized to h'00 upon reset. ? 16-bit mode (tcf) when cksh2 is cleared to 0 in tcrf, tcf operates as a 16-bit counter. the tcf input clock is selected by bits cksl2 to cksl0 in tcrf. tcf can be cleared in the event of a compare match by means of cclrh in tcsrf. when tcf overflows from h'ffff to h'0000, ovfh is set to 1 in tcsrf. if ovieh in tcsrf is 1 at this time, irrtfh is set to 1 in irr2, and if ientfh in ienr2 is 1, an interrupt request is sent to the cpu. ? 8-bit mode (tcfl/tcfh) when cksh2 is set to 1 in tcrf, tcfh and tcfl operate as two independent 8-bit counters. the tcfh (tcfl) input clock is selected by bits cksh2 to cksh0 (cksl2 to cksl0) in tcrf. tcfh (tcfl) can be cleared in the event of a compare match by means of cclrh (cclrl) in tcsrf. when tcfh (tcfl) overflows from h'ff to h'00, ovfh (ovfl) is set to 1 in tcsrf. if ovieh (oviel) in tcsrf is 1 at this time, irrtfh (irrtfl) is set to 1 in irr2, and if ientfh (ientfl) in ienr2 is 1, an interrupt request is sent to the cpu. output compare registers fh and fl (ocrfh, ocrfl): ocrf is a 16-bit read/write register composed of the two registers ocrfh and ocrfl. in addition to the use of ocrf as a 16-bit register with ocrfh as the upper 8 bits and ocrfl as the lower 8 bits, ocrfh and ocrfl can also be used as independent 8-bit registers.
rev. 4.00, 03/04, page 206 of 462 ocrfh and ocrfl can be read and written by the cpu, but when they are used in 16-bit mode, data transfer to and from the cpu is performed via a temporary register (temp). for details of temp, see section 9.3.4, cpu interface. ocrfh and ocrfl are initialized to h'ff upon reset. ? 16-bit mode (ocrf) when cksh2 is cleared to 0 in tcrf, ocrf operates as a 16-bit register. ocrf contents are constantly compared with tcf, and when both values match, cmfh is set to 1 in tcsrf. at the same time, irrtfh is set to 1 in irr2. if ientfh in ienr2 is 1 at this time, an interrupt requestissenttothecpu. toggle output can be provided from the tmofh pin by means of compare matches, and the output level can be set (high or low) by means of tolh in tcrf. ? 8-bit mode (ocrfh/ocrfl) whencksh2issetto1intcrf,ocrfhandocrfloperateastwoindependent8-bit registers. ocrfh contents are compared with tcfh, and ocrfl contents are with tcfl. when the ocrfh (ocrfl) and tcfh (tcfl) values match, cmfh (cmfl) is set to 1 in tcsrf. at the same time, irrtfh (irrtfl) is set to 1 in irr2. if ientfh (ientfl) in ienr2 is 1 at this time, an interrupt request is sent to the cpu. toggle output can be provided from the tmofh pin (tmofl pin) by means of compare matches, and the output level can be set (high or low) by means of tolh (toll) in tcrf. timer control register f (tcrf): tcrf switches between 16-bit mode and 8-bit mode, selects the input clock from among four internal clock sources, and sets the output level of the tmofh and tmofl pins. bit bit name initial value r/w description 7 tolh 0 w toggle output level h sets the tmofh pin output level. 0: low level 1: high level 6 5 4 cksh2 cksh1 cksh0 0 0 0 w w w clock select h select the clock input to tcfh from among four internal clock sources or tcfl overflow. 000: 16-bit mode, counting on tcfl overflow signal 001: 16-bit mode, counting on tcfl overflow signal 010: 16-bit mode, counting on tcfl overflow signal 011: using prohibited 100: internal clock: counting on /32 101: internal clock: counting on /16 110: internal clock: counting on /4 111: internal clock: counting on w /4
rev. 4.00, 03/04, page 207 of 462 bit bit name initial value r/w description 3 toll 0 w toggle output level l sets the tmofl pin output level. 0: low level 1: high level 2 1 0 cksl2 cksl1 cksl0 0 0 0 w w w clock select l select the clock input to tcfl from among four internal clock sources or external event input. 000: non-operational 001: using prohibited 010: using prohibited 011: using prohibited 100: internal clock: counting on /32 101: internal clock: counting on /16 110: internal clock: counting on /4 111: internal clock: counting on w /4 timer control status register f (tcsrf): tcsrf performs counter clear selection, overflow flag setting, and compare match flag setting, and controls enabling of overflow interrupt requests. bit bit name initial value r/w description 7ovfh0 r/w * timer overflow flag h [setting condition] when tcfh overflows from h?ff to h?00 [clearing condition] when this bit is written to 0 after reading ovfh = 1 6cmfh0 r/w * compare match flag h this is a status flag indicating that tcfh has matched ocrfh. [setting condition] when the tcfh value matches the ocrfh value [clearing condition] when this bit is written to 0 after reading cmfh = 1
rev. 4.00, 03/04, page 208 of 462 bit bit name initial value r/w description 5 ovieh 0 r/w timer overflow interrupt enable h selects enabling or disabling of interrupt generation when tcfh overflows. 0: tcfh overflow interrupt request is disabled 1: tcfh overflow interrupt request is enabled 4 cclrh 0 r/w counter clear h in 16-bit mode, this bit selects whether tcf is cleared when tcf and ocrf match. in 8-bit mode, this bit selects whether tcfh is cleared when tcfh and ocrfh match. in 16-bit mode: 0: tcf clearing by compare match is disabled 1: tcf clearing by compare match is enabled in 8-bit mode: 0: tcfh clearing by compare match is disabled 1: tcfh clearing by compare match is enabled 3ovfl0 r/w * timer overflow flag l this is a status flag indicating that tcfl has overflowed. [setting condition] when tcfl overflows from h?ff to h?00 [clearing condition] when this bit is written to 0 after reading ovfl = 1 2cmfl0 r/w * compare match flag l this is a status flag indicating that tcfl has matched ocrfl. [setting condition] when the tcfl value matches the ocrfl value [clearing condition] when this bit is written to 0 after reading cmfl = 1
rev. 4.00, 03/04, page 209 of 462 bit bit name initial value r/w description 1 oviel 0 r/w timer overflow interrupt enable l selects enabling or disabling of interrupt generation when tcfl overflows. 0: tcfl overflow interrupt request is disabled 1: tcfl overflow interrupt request is enabled 0 cclrl 0 r/w counter clear l selects whether tcfl is cleared when tcfl and ocrfl match. 0: tcfl clearing by compare match is disabled 1: tcfl clearing by compare match is enabled note: * only 0 can be written to clear the flag. 9.3.4 cpu interface tcf and ocrf are 16-bit readable/writable registers, but the cpu is connected to the on-chip peripheral modules by an 8-bit data bus. when the cpu accesses these registers, it therefore uses an 8-bit temporary register (temp). in 16-bit mode, tcf read/write access and ocrf write access must be performed 16 bits at a time (using two consecutive byte-size mov instructions), and the upper byte must be accessed before the lower byte. data will not be transferred correctly if only the upper byte or only the lower byte is accessed. in 8-bit mode, there are no restrictions on the order of access. write access: write access to the upper byte results in transfer of the upper-byte write data to temp. next, write access to the lower byte results in transfer of the data in temp to the upper register byte, and direct transfer of the lower-byte write data to the lower register byte. figure 9.3 shows an example in which h'aa55 is written to tcf.
rev. 4.00, 03/04, page 210 of 462 write to upper byte cpu [h'aa] temp [h'aa] tcfh [ ] tcfl [ ] bus interface bus interface module data bus module data bus write to lower byte cpu [h'55] temp [h'aa] tcfh [h'aa] tcfl [h'55] figure 9.3 write access to tcf (cpu tcf) read access: in access to tcf, when the upper byte is read the upper-byte data is transferred directly to the cpu and the lower-byte data is transferred to temp. next, when the lower byte is read, the lower-byte data in temp is transferred to the cpu. in access to ocrf, when the upper byte is read the upper-byte data is transferred directly to the cpu. when the lower byte is read, the lower-byte data is transferred directly to the cpu. figure 9.4 shows an example in which tcf is read when it contains h'aaff.
rev. 4.00, 03/04, page 211 of 462 read upper byte cpu [h'aa] temp [h'ff] tcfh [h'aa] tcfl [h'ff] bus interface module data bus bus interface ** module data bus read lower byte cpu [h'ff] temp [h'ff] tcfh [ab] tcfl [00] note: ? h'ab00 if counter has been updated once. figure 9.4 read access to tcf (tcf cpu) 9.3.5 operation the timer f is a 16-bit counter that increments on each input clock pulse. the timer f value is constantly compared with the value set in the output compare register f, and the counter can be cleared, an interrupt requested, or port output toggled, when the two values match. the timer f can also function as two independent 8-bit timers. timer f operation: the timer f has two operating modes, 16-bit timer mode and 8-bit timer mode. the operation in each of these modes is described below. ? operation in 16-bit timer mode when cksh2 is cleared to 0 in timer control register f (tcrf), timer f operates as a 16-bit timer. following a reset, timer counter f (tcf) is initialized to h'0000, output compare register f (ocrf) to h'ffff, and timer control register f (tcrf) and timer control/status register f (tcsrf) to h'00.
rev. 4.00, 03/04, page 212 of 462 the timer f operating clock can be selected from three internal clocks output by prescaler s by means of bits cksl2 to cksl0 in tcrf. ocrf contents are constantly compared with tcf, and when both values match, cmfh is set to 1 in tcsrf. if ientfh in ienr2 is 1 at this time, an interrupt request is sent to the cpu, and at the same time, tmofh pin output is toggled. if cclrh in tcsrf is 1, tcf is cleared. tmofh pin output can also be set by tolh in tcrf. when tcf overflows from h'ffff to h'0000, ovfh is set to 1 in tcsrf. if ovieh in tcsrf and ientfh in ienr2 are both 1, an interrupt request is sent to the cpu. ? operation in 8-bit timer mode when cksh2 is set to 1 in tcrf, tcf operates as two independent 8-bit timers, tcfh and tcfl. the tcfh/tcfl input clock is selected by cksh2 to cksh0/cksl2 to cksl0 in tcrf. when the ocrfh/ocrfl and tcfh/tcfl values match, cmfh/cmfl is set to 1 in tcsrf. if ientfh/ientfl in ienr2 is 1, an interrupt request is sent to the cpu, and at the same time, tmofh pin/tmofl pin output is toggled. if cclrh/cclrl in tcsrf is 1, tcfh/tcfl is cleared. tmofh pin/tmofl pin output can also be set by tolh/toll in tcrf. when tcfh/tcfl overflows from h'ff to h'00, ovfh/ovfl is set to 1 in tcsrf. if ovieh/oviel in tcsrf and ientfh/ientfl in ienr2 are both 1, an interrupt request is sent to the cpu. tcf increment timing: tcf is incremented by clock input (internal clock input). bits cksh2 to cksh0 or cksl2 to cksl0 in tcrf select one of four internal clock sources ( /32, /16, /4, or w /4) created by dividing the system clock ( or w ). tmofh/tmofl output timing: in tmofh/tmofl output, the value set in tolh/toll in tcrf is output. the output is toggled by the occurrence of a compare match. figure 9.5 shows the output timing.
rev. 4.00, 03/04, page 213 of 462 count input clock tcf ocrf tmofh, tmofl compare match signal nn n n n+1 n+1 figure 9.5 tmofh/tmofl output timing tcf clear timing: tcf can be cleared by a compare match with ocrf. timer overflow flag (ovf) set timing: ovf is set to 1 when tcf overflows from h'ffff to h'0000. compare match flag set timing: the compare match flag (cmfh or cmfl) is set to 1 when the tcf and ocrf values match. the compare match signal is generated in the last state during which the values match (when tcf is updated from the matching value to a new value). when tcf matches ocrf, the compare match signal is not generated until the next counter clock.
rev. 4.00, 03/04, page 214 of 462 9.3.6 timer f operating states the timer f operating states are shown in table 9.4. table 9.4 timer f operating states operating mode reset active sleep watch sub-active sub-sleep standby module standby tcf reset functions * functions * functions/ halted * functions/ halted * functions/ halted * halted halted ocrf reset functions retained retained functions retained retained retained tcrf reset functions retained retained functions retained retained retained tcsrf reset functions retained retained functions retained retained retained note: * when w /4 is selected as the tcf internal clock in active mode or sleep mode, since the system clock and internal clock are mutually asynchronous, synchronization is maintained by a synchronization circuit. this results in a maximum count cycle error of 1/ (s). when the counter is operated in subactive mode, watch mode, or subsleep mode, w /4 must be selected as the internal clock. the counter will not operate if any other internal clock is selected. 9.3.7 usage notes the following types of contention and operation can occur when the timer f is used. 16-bit timer mode: in toggle output, tmofh pin output is toggled when all 16 bits match and a compare match signal is generated. if a tcrf write by a mov instruction and generation of the compare match signal occur simultaneously, tolh data is output to the tmofh pin as a result of the tcrf write. tmofl pin output is unstable in 16-bit mode, and should not be used; the tmofl pin should be used as a port pin. if an ocrfl write and compare match signal generation occur simultaneously, the compare match signal is invalid. however, if the written data and the counter value match, a compare match signal will be generated at that point. as the compare match signal is output in synchronization with the tcfl clock, a compare match will not result in compare match signal generation if the clock is stopped. compare match flag cmfh is set when all 16 bits match and a compare match signal is generated. compare match flag cmfl is set if the setting conditions for the lower 8 bits are satisfied. when tcf overflows, ovfh is set. ovfl is set if the setting conditions are satisfied when the lower 8 bits overflow. if a tcfl write and overflow signal output occur simultaneously, the overflow signal is not output.
rev. 4.00, 03/04, page 215 of 462 8-bit timer mode: ? tcfh, ocrfh in toggle output, tmofh pin output is toggled when a compare match occurs. if a tcrf write by a mov instruction and generation of the compare match signal occur simultaneously, tolh data is output to the tmofh pin as a result of the tcrf write. if an ocrfh write and compare match signal generation occur simultaneously, the compare match signal is invalid. however, if the written data and the counter value match, a compare match signal will be generated at that point. the compare match signal is output in synchronization with the tcfh clock. if a tcfh write and overflow signal output occur simultaneously, the overflow signal is not output. ? tcfl, ocrfl in toggle output, tmofl pin output is toggled when a compare match occurs. if a tcrf write by a mov instruction and generation of the compare match signal occur simultaneously, toll data is output to the tmofl pin as a result of the tcrf write. if an ocrfl write and compare match signal generation occur simultaneously, the compare match signal is invalid. however, if the written data and the counter value match, a compare match signal will be generated at that point. as the compare match signal is output in synchronization with the tcfl clock, a compare match will not result in compare match signal generation if the clock is stopped. if a tcfl write and overflow signal output occur simultaneously, the overflow signal is not output. clear timer fh, timer fl interrupt request flags (irrtfh, irrtfl), timer overflow flags h, l (ovfh, ovfl), and compare match flags h, l (cmfh, cmfl): when w /4 is selected as the internal clock, ?interrupt source generation signal? will be operated with w and the signal will be outputted with w width. and, ?overflow signal? and ?compare match signal? are controlled with 2 cycles of w signals. those signals are outputted with 2 cycles width of w (figure 9.6) in active (high-speed, medium-speed) mode, even if you cleared interrupt request flag during the term of validity of ?interrupt source generation signal?, same interrupt request flag is set. (1 in figure 9.6) and, the timer overflow flag and compare match flag cannot be cleared during the term of validity of ?overflow signal? and ?compare match signal?. for interrupt request flag is set right after interrupt request is cleared, interrupt process to one time timer fh, timer fl interrupt might be repeated. (2 in figure 9.6) therefore, to definitely clear interrupt request flag in active (high-speed, medium-speed) mode, clear should be processed after the time that calculated with below (1) formula. and, to definitely clear timer overflow flag and compare match flag, clear should be processed after read timer control status register f (tcsrf) after the time that calculated with below (1) formula.
rev. 4.00, 03/04, page 216 of 462 for st of (1) formula, please substitute the longest number of execution states in used instruction. (10 states of rte instruction when mulxu, divxu instruction is not used, 14 states when mulxu, divxu instruction is used) in subactive mode, there are not limitation for interrupt request flag, timer overflow flag, and compare match flag clear. the term of validity of ?interrupt source generation signal? = 1 cycle of w + waiting time for completion of executing instruction + interrupt time synchronized with =1/ w +st (1/ )+(2/ ) (second).....(1) st: executing number of execution states method 1 is recommended to operate for time efficiency. method 1 1. prohibit interrupt in interrupt handling routine (set ienfh, ienfl to 0). 2. after program process returned normal handling, clear interrupt request flags (irrtfh, irrtfl) after more than that calculated with (1) formula. 3. after reading the timer control status register f (tcsrf), clear the timer overflow flags (ovfh, ovfl) and compare match flags (cmfh, cmfl). 4. enable interrupts (set ienfh, ienfl to 1). method 2 1. set interrupt handling routine time to more than time that calculated with (1) formula. 2. clear interrupt request flags (irrtfh, irrtfl) at the end of interrupt handling routine. 3. after read timer control status register f (tcsrf), clear timer overflow flags (ovfh, ovfl) and compare match flags (cmfh, cmfl). all above attentions are also applied in 16-bit mode and 8-bit mode.
rev. 4.00, 03/04, page 217 of 462 w program processing interrupt source generation signal (internal signal, nega-active) overflow signal, compare match signal (internal signal, nega-active) interrupt request flag (irrtfh, irrtfl) interrupt normal interrupt request flag clear 2 interrupt interrupt request flag clear 1 figure 9.6 clear interrupt request flag when interrupt source generation signal is valid timer counter (tcf) read/write: when w /4 is selected as the internal clock in active (high- speed, medium-speed) mode, write on tcf is impossible. and when reading tcf, as the system clock and internal clock are mutually asynchronous, tcf synchronizes with synchronization circuit. this results in a maximum tcf read value error of 1. when reading or writing tcf in active (high-speed, medium-speed) mode is needed, please select the internal clock except for w /4 before read/write is performed. in subactive mode, even if w /4 is selected as the internal clock, tcf can be read from or written to normally.
rev. 4.00, 03/04, page 218 of 462 9.4 asynchronous event counter (aec) the asynchronous event counter is incremented by external event clock or internal clock input. figure 9.7 shows a block diagram of the asynchronous event counter. 9.4.1 features ? can count asynchronous events can count external events input asynchronously without regard to the operation of system clocks and sub ? can be used as two-channel independent 8-bit event counter or single-channel independent 16- bit event counter. ? event/clock input is enabled only when irqaec is high or event counter pwm output (iecpwm) is high. ? both edge sensing can be used for irqaec or event counter pwm output (iecpwm) interrupts. when the asynchronous counter is not used, they can be used as independent interrupts. ? when an event counter pwm is used, event clock input enabling/disabling can be controlled automatically in a fixed cycle. ? external event input or a prescaler output clock can be selected by software for the ech and ecl clock sources. /2, /4, or /8 can be selected as the prescaler output clock. ? both edge counting is possible for aevl and aevh. ? counter resetting and halting of the count-up function can be controlled by software ? automatic interrupt generation on detection of an event counter overflow ? use of module standby mode enables this module to be placed in standby mode independently when not used. (for details, refer to section 5.4, module standby function.)
rev. 4.00, 03/04, page 219 of 462 aevh aevl irqaec iecpwm eccr pss eccsr internal data bus ovh ovl ecpwcrh ecpwdrh aegsr ecpwcrl ecpwdrl ech (8 bits) ck ecl (8 bits) ck irrec to cpu interrupt (irrec2) edge sensing circuit edge sensing circuit edge sensing circuit pwm waveform generator /2 /4, /8 /2, /4, /8, /16, /32, /64 [legend] ecpwcrh ecpwdrh aegsr eccsr ecl : event counter pwm compare register h : event counter pwm data register h : input pin edge select register : event counter control/status register : event counter l ecpwcrl ecpwdrl eccr ech : event counter pwm compare register l : event counter pwm data register l : event counter control register : event counter h figure 9.7 block diagram of asynchronous event counter
rev. 4.00, 03/04, page 220 of 462 9.4.2 input/output pins table 9.5 shows the pin configuration of the asynchronous event counter. table 9.5 pin configuration name abbreviation i/o function asynchronous event input h aevh input event input pin for input to event counter h asynchronous event input l aevl input event input pin for input to event counter l event input enable interrupt input irqaec input input pin for interrupt enabling event input 9.4.3 register descriptions the asynchronous event counter has the following registers. ? event counter pwm compare register h (ecpwcrh) ? event counter pwm compare register l (ecpwcrl) ? event counter pwm data register h (ecpwdrh) ? event counter pwm data register l (ecpwdrl) ? input pin edge select register (aegsr) ? event counter control register (eccr) ? event counter control/status register (eccsr) ? event counter h (ech) ? event counter l (ecl)
rev. 4.00, 03/04, page 221 of 462 event counter pwm compare register h (ecpwcrh): ecpwcrh sets the one conversion period of the event counter pwm waveform. bit bit name initial value r/w description 7 ecpwcrh7 1 r/w 6 ecpwcrh6 1 r/w 5 ecpwcrh5 1 r/w 4 ecpwcrh4 1 r/w 3 ecpwcrh3 1 r/w 2 ecpwcrh2 1 r/w 1 ecpwcrh1 1 r/w 0 ecpwcrh0 1 r/w one conversion period of event counter pwm waveform note: when ecpwme in aegsr is 1, the event counter pwm is operating and therefore ecpwcrh should not be modified. when changing the conversion period, the event counter pwm must be halted by clearing ecpwme to 0 in aegsr before modifying ecpwcrh. event counter pwm compare register l (ecpwcrl): ecpwcrl sets the one conversion period of the event counter pwm waveform. bit bit name initial value r/w description 7 ecpwcrl7 1 r/w 6 ecpwcrl6 1 r/w 5 ecpwcrl5 1 r/w 4 ecpwcrl4 1 r/w 3 ecpwcrl3 1 r/w 2 ecpwcrl2 1 r/w 1 ecpwcrl1 1 r/w 0 ecpwcrl0 1 r/w one conversion period of event counter pwm waveform note: when ecpwme in aegsr is 1, the event counter pwm is operating and therefore ecpwcrl should not be modified. when changing the conversion period, the event counter pwm must be halted by clearing ecpwme to 0 in aegsr before modifying ecpwcrl.
rev. 4.00, 03/04, page 222 of 462 event counter pwm data register h (ecpwdrh): ecpwdrh controls data of the event counter pwm waveform generator. bit bit name initial value r/w description 7 ecpwdrh7 0 w 6 ecpwdrh6 0 w 5 ecpwdrh5 0 w 4 ecpwdrh4 0 w 3 ecpwdrh3 0 w 2 ecpwdrh2 0 w 1 ecpwdrh1 0 w 0 ecpwdrh0 0 w data control of event counter pwm waveform generator note: when ecpwme in aegsr is 1, the event counter pwm is operating and therefore ecpwdrh should not be modified. when changing the data, the event counter pwm must be halted by clearing ecpwme to 0 in aegsr before modifying ecpwdrh. event counter pwm data register l (ecpwdrl): ecpwdrl controls data of the event counter pwm waveform generator. bit bit name initial value r/w description 7 ecpwdrl7 0 w 6 ecpwdrl6 0 w 5 ecpwdrl5 0 w 4 ecpwdrl4 0 w 3 ecpwdrl3 0 w 2 ecpwdrl2 0 w 1 ecpwdrl1 0 w 0 ecpwdrl0 0 w data control of event counter pwm waveform generator note: when ecpwme in aegsr is 1, the event counter pwm is operating and therefore ecpwdrl should not be modified. when changing the data, the event counter pwm must be halted by clearing ecpwme to 0 in aegsr before modifying ecpwdrl.
rev. 4.00, 03/04, page 223 of 462 input pin edge select register (aegsr): aegsr selects rising, falling, or both edge sensing for the aevh, aevl, and irqaec pins. bit bit name initial value r/w description 7 6 ahegs1 ahegs0 0 0 r/w r/w aec edge select h select rising, falling, or both edge sensing for the aevh pin. 00: falling edge on aevh pin is sensed 01: rising edge on aevh pin is sensed 10: both edges on aevh pin are sensed 11: setting prohibited 5 4 alegs1 alegs0 0 0 r/w r/w aec edge select l select rising, falling, or both edge sensing for the aevl pin. 00: falling edge on aevl pin is sensed 01: rising edge on aevl pin is sensed 10: both edges on aevl pin are sensed 11: setting prohibited 3 2 aiegs1 aiegs0 0 0 r/w r/w irqaec edge select select rising, falling, or both edge sensing for the irqaec pin. 00: falling edge on irqaec pin is sensed 01: rising edge on irqaec pin is sensed 10: both edges on irqaec pin are sensed 11: setting prohibited 1 ecpwme 0 r/w event counter pwm enable controls operation of event counter pwm and selection of irqaec. 0: aec pwm halted, irqaec selected 1: aec pwm enabled, irqaec not selected 0 ? 0r/wreserved this bit can be read from or written to. however, this bit should not be set to 1.
rev. 4.00, 03/04, page 224 of 462 event counter control register (eccr): eccr controls the counter input clock and irqaec/iecpwm. bit bit name initial value r/w description 7 6 ackh1 ackh0 0 0 r/w r/w aec clock select h select the clock used by ech. 00: aevh pin input 01: /2 10: /4 11: /8 5 4 ackl1 ackl0 0 0 r/w r/w aec clock select l select the clock used by ecl. 00: aevl pin input 01: /2 10: /4 11: /8 3 2 1 pwck2 pwck1 pwck0 0 0 0 r/w r/w r/w event counter pwm clock select select the event counter pwm clock. 000: /2 001: /4 010: /8 011: /16 1x0: /32 1x1 /64 0 ? 0r/wreserved this bit can be read from or written to. however, this bit should not be set to 1. [legend] x: don't care.
rev. 4.00, 03/04, page 225 of 462 event counter control/status register (eccsr): eccsr controls counter overflow detection, counter clear resetting, and the count-up function. bit bit name initial value r/w description 7ovh0 r/w * counter overflow h this is a status flag indicating that ech has overflowed. [setting condition] when ech overflows from h?ff to h?00 [clearing condition] when this bit is written to 0 after reading ovh = 1 6ovl 0 r/w * counter overflow l this is a status flag indicating that ecl has overflowed. [setting condition] when ecl overflows from h'ff to h'00 [clearing condition] when this bit is written to 0 after reading ovl = 1 5 ? 0r/wreserved this bit can be read from or written to. however, the initial value should not be changed. 4 ch2 0 r/w channel select selects how ech and ecl event counters are used 0: ech and ecl are used together as a single-channel 16-bit event counter 1: ech and ecl are used as two-channel 8-bit event counter 3 cueh 0 r/w count-up enable h enables event clock input to ech. 0: ech event clock input is disabled (ech value is retained) 1: ech event clock input is enabled 2 cuel 0 r/w count-up enable l enables event clock input to ecl. 0: ecl event clock input is disabled (ecl value is retained) 1: ecl event clock input is enabled
rev. 4.00, 03/04, page 226 of 462 bit bit name initial value r/w description 1 crch 0 r/w counter reset control h controls resetting of ech. 0: ech is reset 1: ech reset is cleared and count-up function is enabled 0 crcl 0 r/w counter reset control l controls resetting of ecl. 0: ecl is reset 1: ecl reset is cleared and count-up function is enabled note: * only 0 can be written to clear the flag. event counter h (ech): ech is an 8-bit read-only up-counter that operates as an independent 8-bit event counter. ech also operates as the upper 8-bit up-counter of a 16-bit event counter configured in combination with ecl. bit bit name initial value r/w description 7 ech7 0 r 6 ech6 0 r 5 ech5 0 r 4 ech4 0 r 3 ech3 0 r 2 ech2 0 r 1 ech1 0 r 0 ech0 0 r either the external asynchronous event aevh pin, /2, /4, or /8, or the overflow signal from lower 8-bit counter ecl can be selected as the input clock source. ech can be cleared to h'00 by software.
rev. 4.00, 03/04, page 227 of 462 event counter l (ecl): ecl is an 8-bit read-only up-counter that operates as an independent 8- bit event counter. ecl also operates as the upper 8-bit up-counter of a 16-bit event counter configured in combination with ech. bit bit name initial value r/w description 7ecl70 r 6ecl60 r 5ecl50 r 4ecl40 r 3ecl30 r 2ecl20 r 1ecl10 r 0ecl00 r either the external asynchronous event aevl pin, /2, /4, or /8 can be selected as the input clock source. ecl can be cleared to h'00 by software. 9.4.4 operation 16-bit counter operation: when bit ch2 is cleared to 0 in eccsr, ech and ecl operate as a 16-bit event counter. any of four input clock sources? /2, /4, /8, or aevl pin input?can be selected by means of bits ackl1 and ackl0 in eccr. when aevl pin input is selected, input sensing is selected with bits alegs1 and alegs0. the input clock is enabled only when irqaec is high or iecpwm is high. when irqaec is low or iecpwm is low, the input clock is not input to the counter, which therefore does not operate. figure 9.8 shows an example of the software processing when ech and ecl are used as a 16-bit event counter.
rev. 4.00, 03/04, page 228 of 462 clear ch2 to 0 set ackl1, ackl0, alegs1, and alegs0 clear cueh, cuel, crch, and crcl to 0 clear ovh and ovl to 0 set cueh, cuel, crch, and crcl to 1 start end figure 9.8 example of software processing when using ech and ecl as 16-bit event counter as ch2 is cleared to 0 by a reset, ech and ecl operate as a 16-bit event counter after a reset, and as ackl1 and ackl0 are cleared to b 00, the operating clock is asynchronous event input from the aevl pin (using falling edge sensing). when the next clock is input after the count value reaches h'ff in both ech and ecl, ech and ecl overflow from h'ffff to h'0000, the ovh flag is set to 1 in eccsr, the ech and ecl count values each return to h'00, and counting up is restarted. when overflow occurs, the irrec bit is set to 1 in irr2. if the ienec bit in ienr2 is 1 at this time, an interrupt request is sent to the cpu. 8-bit counter operation: whenbitch2issetto1ineccsr,echandecloperateas independent 8-bit event counters. /2, /4, /8, or aevh pin input can be selected as the input clock source for ech by means of bits ackh1 and ackh0 in eccr, and /2, /4, /8, or aevl pin input can be selected as the input clock source for ecl by means of bits ackl1 and ackl0 in eccr. input sensing is selected with bits ahegs1 and ahegs0 when aevh pin input is selected, and with bits alegs1 and alegs0 when aevl pin input is selected. the input clock is enabled only when irqaec is high or iecpwm is high. when irqaec is low or iecpwm is low, the input clock is not input to the counter, which therefore does not operate. figure 9.9 shows an example of the software processing when ech and ecl are used as 8-bit event counters.
rev. 4.00, 03/04, page 229 of 462 set ch2 to 1 set ackh1, ackh0, ackl1, ackl0, ahegs1, ahegs0, alegs1, and alegs0 clear cueh, cuel, crch, and crcl to 0 clear ovh and ovl to 0 set cueh, cuel, crch, and crcl to 1 start end figure 9.9 example of software processing when using ech and ecl as 8-bit event counters ech and ecl can be used as 8-bit event counters by carrying out the software processing shown in the example in figure 9.9. when the next clock is input after the ech count value reaches h'ff, ech overflows, the ovh flag is set to 1 in eccsr, the ech count value returns to h'00, and counting up is restarted. similarly, when the next clock is input after the ecl count value reaches h'ff, ecl overflows, the ovl flag is set to 1 in eccsr, the ecl count value returns to h'00, and counting up is restarted. when an overflow occurs, the irrec bit is set to 1 in irr2. if the ienec bit in ienr2 is 1 at this time, an interrupt request is sent to the cpu. irqaec operation: when ecpwme in aegsr is 0, the ech and ecl input clocks are enabled only when irqaec is high. when irqaec is low, the input clocks are not input to the counters, and so ech and ecl do not count. ech and ecl count operations can therefore be controlled from outside by controlling irqaec. in this case, ech and ecl cannot be controlled individually. irqaec can also operate as an interrupt source. in this case the vector number is 6 and the vector addresses are h'000c and h'000d. interrupt enabling is controlled by ienec2 in ienr1. when an irqaec interrupt is generated, irr1 interrupt request flag irrec2 is set to 1. if ienec2 in ienr1 is set to 1 at this time, an interrupt request is sent to the cpu. rising, falling, or both edge sensing can be selected for the irqaec input pin with bits aiags1 andaiags0inaegsr. note: on the h8/38104 group, control of switching between the system clock oscillator and the on-chip oscillator during resets should be performed by setting the irqaec input level. refer to section 4.4, subclock generator, for details.
rev. 4.00, 03/04, page 230 of 462 event counter pwm operation: when ecpwme in aegsr is 1, the ech and ecl input clocks are enabled only when event counter pwm output (iecpwm) is high. when iecpwm is low, the input clocks are not input to the counters, and so ech and ecl do not count. ech and ecl count operations can therefore be controlled cyclically from outside by controlling event counter pwm. in this case, ech and ecl cannot be controlled individually. iecpwm can also operate as an interrupt source. in this case the vector number is 6 and the vector addresses are h'000c and h'000d. interrupt enabling is controlled by ienec2 in ienr1. when an iecpwm interrupt is generated, irr1 interrupt request flag irrec2 is set to 1. if ienec2 in ienr1 is set to 1 at this time, an interrupt request is sent to the cpu. rising, falling, or both edge detection can be selected for iecpwm interrupt sensing with bits aiags1 and aiags0 in aegsr. figure 9.10 and table 9.6 show examples of event counter pwm operation. t off = t (n dr +1) t on t cm = t (n cm +1) t on t off t cm t n dr n cm : clock input enable time : clock input disable time : one conversion period : ecpwm input clock cycle : value of ecpwdrh and ecpwdrl fixed high when ndr = h'ffff : value of ecpwcrh and ecpwcrl figure 9.10 event counter operation waveform note: ndr and ncm above must be set so that ndr < ncm. if the settings do not satisfy this condition, do not set ecpwme to 1 in aegsr.
rev. 4.00, 03/04, page 231 of 462 table 9.6 examples of event counter pwm operation conditions: fosc = 4 mhz, f = 2 mhz, high-speed active mode, ecpwcr value (ncm) = h'7a11, ecpwdr value (ndr) = h'16e3 clock source selection clock source cycle (t) * ecpwmcr value (ncm) ecpwmdr value (ndr) toff = t (ndr + 1) tcm = t (ncm + 1) ton = tcm ? toff /2 1 s 5.86 ms 31.25 ms 25.39 ms /4 2 s 11.72 ms 62.5 ms 50.78 ms /8 4 s 23.44 ms 125.0 ms 101.56 ms /16 8 s 46.88 ms 250.0 ms 203.12 ms /32 16 s 93.76 ms 500.0 ms 406.24 ms /64 32 s h'7a11 d'31249 h'16e3 d'5859 187.52 ms 1000.0 ms 812.48 ms note: * toff minimum width clock input enable/disable function operation: the clock input to the event counter can be controlled by the irqaec pin when ecpwme in aegsr is 0, and by the event counter pwm output, iecpwm when ecpwme in aegsr is 1. as this function forcibly terminates the clock input by each signal, a maximum error of one count will occur depending on the irqaec or iecpwm timing. figure 9.11 shows an example of the operation of this function. clock stopped n+2 n+3 n+4 n+5 n+6 n n+1 edge generated by clock return input event irqaec or iecpwm actually counted clock source counter value figure 9.11 example of clock control operation
rev. 4.00, 03/04, page 232 of 462 9.4.5 operating states of asynchronous event counter the operating states of the asynchronous event counter are shown in table 9.7. table 9.7 operating states of asynchronous event counter operating mode reset active sleep watch sub-active sub-sleep standby module standby aegsr reset functions functions retained * 1 functions functions retained * 1 retained eccr reset functions functions retained * 1 functions functions retained * 1 retained eccsr reset functions functions retained * 1 functions functions retained * 1 retained ech reset functions functions functions * 1 * 2 functions * 2 functions * 2 functions * 1 * 2 halted ecl reset functions functions functions * 1 * 2 functions * 2 functions * 2 functions * 1 * 2 halted irqaec reset functions functions retained * 3 functions functions retained * 3 retained * 4 event counter pwm reset functions functions retained retained retained retained retained notes: 1. when an asynchronous external event is input, the counter increments but the counter overflow h/l flags are not affected. 2. functions when asynchronous external events are selected; halted and retained otherwise. 3. clock control by irqaec operates, but interrupts do not. 4. as the clock is stopped in module standby mode, irqaec has no effect. 9.4.6 usage notes 1. when reading the values in ech and ecl, first clear bits cueh and cuel to 0 in eccsr in 8-bit mode and clear bit cuel to 0 in 16-bit mode to prevent asynchronous event input to the counter. the correct value will not be returned if the event counter increments while being read. 2. use a clock with a frequency of up to 16 mhz * 1 for input to the aevh and aevl pins, and ensure that the high and low widths of the clock are at least 30 ns * 2 .thedutycycleis immaterial.
rev. 4.00, 03/04, page 233 of 462 mode maximum clock frequency input to aevh/aevl pin active (high-speed), sleep (high-speed) 16 mhz * 1 active (medium-speed), sleep (medium-speed) ( /16) ( /32) ( /64) f osc = 1 mhz to 4 mhz ( /128) 2f osc f osc 1/2 f osc 1/4 f osc watch, subactive, subsleep, standby ( w /2) ( w /4) w = 32.768 khz or 38.4 khz ( w /8) 1000 khz 500 khz 250 khz notes: 1. up to 10 mhz in the h8/38004 group. 2. at least 50 ns in the h8/38004 group. 3. when aec uses with 16-bit mode, set cueh in eccsr to 1 first, set crch in eccsr to 1 second, or set both cueh and crch to 1 at same time before clock input. while aec is operating on 16-bit mode, do not change cueh. otherwise, ech will be miscounted up. 4. when ecpwme in aegsr is 1, the event counter pwm is operating and therefore ecpwcrh, ecpwcrl, ecpwdrh, and ecpwdrl should not be modified. when changing the data, the event counter pwm must be halted by clearing ecpwme to 0 in aegsr before modifying these registers. 5. the event counter pwm data register and event counter pwm compare register must be set so that event counter pwm data register < event counter pwm compare register. if the settings do not satisfy this condition, do not set ecpwme to 1 in aegsr. 6. as synchronization is established internally when an irqaec interrupt is generated, a maximum error of 1 tcyc will occur between clock halting and interrupt acceptance.
rev. 4.00, 03/04, page 234 of 462 9.5 watchdog timer the watchdog timer is an 8-bit timer that can generate an internal reset signal for this lsi if a system crash prevents the cpu from writing to the timer counter, thus allowing it to overflow. however, as shown in watchdog timer block diagrams figure 9.12 (1) and figure 9.12 (2), the implementation differs in the h8/38004 group and the h8/38104 group. 9.5.1 features ? selectable from two counter input clocks (h8/38004 group). two clock sources ( /8192 or w /32) can be selected as the timer-counter clock. ? on the h8/38104 group, 10 internal clocks are available for selection. ten internal clocks ( /64, /128, /256, /512, /1024, /2048, /4096, /8192, w/32, or on-chip oscillator) can be selected as the timer-counter clock. ? reset signal generated on counter overflow an overflow period of 1 to 256 times the selected clock can be set. ? use of module standby mode enables this module to be placed in standby mode independently when not used. (for details, refer to section 5.4, module standby function.) / figure 9.12(1) block diagram of watchdog timer (h8/38004 group)
rev. 4.00, 03/04, page 235 of 462 tcsrw tmw tcw internal data bus pss on-chip oscillator w /32 internal reset signal or interrupt request signal interrupt/reset controller [legend] tcsrw: tcw: tmw: pss: timer control/status register w timer counter w timer mode register w prescaler s figure 9.12(2) block diagram of watchdog timer (h8/38104 group) 9.5.2 register descriptions the watchdog timer has the following registers. ? timer control/status register w (tcsrw) ? timer counter w (tcw) ? timer mode register w (tmw) * note: * this register is implemented on the h8/38104 group only. timer control/status register w (tcsrw): tcsrw performs the tcsrw and tcw write control. tcsrw also controls the watchdog timer operation and indicates the operating state. tcsrw must be rewritten by using the mov instruction. the bit manipulation instruction cannot be used to change the setting value.
rev. 4.00, 03/04, page 236 of 462 bit bit name initial value r/w description 7 b6wi 1 r bit 6 write inhibit the tcwe bit can be written only when the write value of the b6wi bit is 0. this bit is always read as 1. 6tcwe0 r/(w) * 1 timer counter w write enable tcw can be written when the tcwe bit is set to 1. when writing data to this bit, the value for bit 7 must be 0. 5 b4wi 1 r bit 4 write inhibit the tcsrwe bit can be written only when the write value of the b4wi bit is 0. this bit is always read as 1. 4 tcsrwe 0 r/(w) * 1 timer control/status register w write enable the wdon and wrst bits can be written when the tcsrwe bit is set to 1. when writing data to this bit, the value for bit 5 must be 0. 3 b2wi 1 r bit 2 write inhibit this bit can be written to the wdon bit only when the write value of the b2wi bit is 0. this bit is always read as 1. 2wdon0/1 * 2 r/(w) * 1 watchdog timer on tcw starts counting up when wdon is set to 1 and halts when wdon is cleared to 0. [setting condition] when1iswrittentothewdonbitwhilewriting0tothe b2wi bit when the tcsrwe bit=1 [clearing condition] ? res pin * 3 ?
rev. 4.00, 03/04, page 237 of 462 bit bit name initial value r/w description 0wrst0 r/(w) * 1 watchdog timer reset [setting condition] when tcw overflows and an internal reset signal is generated [clearing condition] ? res pin ? timer counter w (tcw): tcw is an 8-bit readable/writable up-counter. when tcw overflows from h'ff to h'00, the internal reset signal is generated and the wrst bit in tcsrw is set to 1. tcw is initialized to h'00. timermoderegisterw(tmw): tmw selects the input clock. clock source selection using this register is enabled when wdcks in port mode register 2 (pmr2) is cleared to 0. if wdcks is set to 1, w/32 is selected as the clock source, regardless of the setting of tmw. note: tmw is implemented on h8/38104 group only. bit bit name initial value r/w description 7to4 ? all 1 ? this bit is reserved. it is always read as 1. 3 2 1 0 cks3 cks2 cks1 cks0 1 1 1 1 r/w r/w r/w r/w clock select 3 to 0 selects the clock input to tcwd. 1000: internal clock: counting on
rev. 4.00, 03/04, page 238 of 462 9.5.3 operation the watchdog timer is provided with an 8-bit counter. the input clock is selected by the wdcks bit in the port mode register 2 (pmr2) * : on the h8/38004 group, /8192 is selected when the wdcks bit is cleared to 0, and w/32 when set to 1. on the h8/38104 group, the clock specified by timer mode register w (tmw) is selected when wdcks is cleared to 0, and w/32 is selected when wdcks is set to 1. if 1 is written to wdon while writing 0 to b2wi when the tcsrwe bit in tcsrw is set to 1, tcw begins counting up. (to operate the watchdog timer, two write accesses to tcsrw are required. however, on the h8/38104 group, tcw begins counting up even if no write access occurs, because wdon is set to 1 when the reset is cleared.) when a clock pulse is input after the tcw count value has reached h'ff, the watchdog timer overflows and an internal reset signal is generated. the internal reset signal is output for a period of 512 osc clock cycles. tcw is a writable counter, and when a value is set in tcw, the count-up starts from that value. an overflow period in the range of 1 to 256 input clock cycles can therefore be set, according to the tcw set value. note: * for details, refer to section 8.1.5, port mode register 2 (pmr2). figure 9.13 shows an example of watchdog timer operation. example: with 30-ms overflow period when = 4 mhz 4 10 6 30 10 ?3 = 14.6 8192 tcw overflow h'ff h'00 internal reset signal h'f1 tcw count value h'f1 written to tcw h'f1 written to tcw reset generated start 512 osc clock cycles therefore, 256 ? 15 = 241 (h'f1) is set in tcw. figure 9.13 example of watchdog timer operation
rev. 4.00, 03/04, page 239 of 462 9.5.4 operating states of watchdog timer tables 9.8(1) and 9.8(2) summarize the operating states of the watchdog timer for the h8/38004 group and h8/38104 group, respectively. table 9.8(1) operating states of watchdog timer (h8/38004 group) operating mode reset active sleep watch sub-active sub-sleep standby module standby tcw reset functions functions halted functions/ halted * halted halted halted tcsrw reset functions functions retained functions/ halted * retained retained retained note: * functions when table 9.8(2) operating states of watchdog timer (h8/38104 group) operating mode reset active sleep watch sub-active sub-sleep standby module standby tcw reset functions functions functions/ halted * 1 functions/ halted * 1 functions/ halted * 1 functions/ halted * 2 halted tcsrw reset functions functions functions/ retained * 1 functions/ halted * 1 functions/ retained * 1 functions/ retained * 2 retained tmw reset functions functions functions/ retained * 1 functions/ halted * 1 functions/ retained * 1 functions/ retained * 2 retained notes: 1. functions when
rev. 4.00, 03/04, page 240 of 462
sci0012a_000020020900 rev. 4.00, 03/04, page 241 of 462 section 10 serial communication interface 3 (sci3) serial communication interface 3 (sci3) can handle both asynchronous and clocked synchronous serial communication. in the asynchronous method, serial data communication can be carried out using standard asynchronous communication chips such as a universal asynchronous receiver/transmitter (uart) or an asynchronous communication interface adapter (acia). a function is also provided for serial communication between processors (multiprocessor communication function). figure 10.1 shows a block diagram of the sci3. 10.1 features ? choice of asynchronous or clocked synchronous serial communication mode ? full-duplex communication capability the transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously. double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data. ? on-chip baud rate generator allows any bit rate to be selected ? external clock or on-chip baud rate generator can be selected as a transfer clock source. ? six interrupt sources transmit-end, transmit-data-empty, receive-data-full, overrun error, framing error, and parity error. note: on the h8/38104 group, the system clock generator must be used when carrying out this function. asynchronous mode ? data length: 7, 8, or 5 bits ? stop bit length: 1 or 2 bits ? parity: even, odd, or none ? receive error detection: parity, overrun, and framing errors ? break detection: break can be detected by reading the rxd32 pin level directly in the case of a framing error clocked synchronous mode ? data length: 8 bits ? receive error detection: overrun errors detected
rev. 4.00, 03/04, page 242 of 462 clock txd32 rxd32 sck 32 brr smr scr3 ssr tdr rdr tsr rsr spcr transmit/receive control circuit internal data bus [legend] rsr: rdr: tsr: tdr: smr: scr3: ssr: brr: brc: spcr: receive shift register receive data register transmit shift register transmit data register serial mode register serial control register 3 serial status register bit rate register bit rate counter serial port control register interrupt request (tei, txi, rxi, eri) internal clock ( /64, /16, w/2, ) external clock brc baud rate generator figure 10.1 block diagram of sci3
rev. 4.00, 03/04, page 243 of 462 10.2 input/output pins table 10.1 shows the sci3 pin configuration. table 10.1 pin configuration pin name abbreviation i/o function sci3 clock sck32 i/o sci3 clock input/output sci3 receive data input rxd32 input sci3 receive data input sci3 transmit data output txd32 output sci3 transmit data output 10.3 register descriptions the sci3 has the following registers. ? receive shift register (rsr) ? receive data register (rdr) ? transmit shift register (tsr) ? transmit data register (tdr) ? serial mode register (smr) ? serial control register 3 (scr3) ? serial status register (ssr) ? bit rate register (brr) ? serial port control register (spcr) 10.3.1 receive shift register (rsr) rsr is a shift register that is used to receive serial data input from the rxd32 pin and convert it into parallel data. when one byte of data has been received, it is transferred to rdr automatically. rsr cannot be directly accessed by the cpu. 10.3.2 receive data register (rdr) rdr is an 8-bit register that stores received data. when the sci3 has received one byte of serial data, it transfers the received serial data from rsr to rdr, where it is stored. after this, rsr is receive-enabled. as rsr and rdr function as a double buffer in this way, continuous receive operations are possible. after confirming that the rdrf bit in ssr is set to 1, read rdr only once. rdr cannot be written to by the cpu. rdr is initialized to h'00 at a reset and in standby, watch, or module standby mode.
rev. 4.00, 03/04, page 244 of 462 10.3.3 transmit shift register (tsr) tsr is a shift register that transmits serial data. to perform serial data transmission, the sci3 first transfers transmit data from tdr to tsr automatically, then sends the data that starts from the lsbtothetxd32pin . data transfer from tdr to tsr is not performed if no data has been written to tdr (if the tdre bit in ssr is set to 1). tsr cannot be directly accessed by the cpu. 10.3.4 transmit data register (tdr) tdr is an 8-bit register that stores data for transmission. when the sci3 detects that tsr is empty, it transfers the transmit data written in tdr to tsr and starts transmission. the double- buffered structure of tdr and tsr enables continuous serial transmission. if the next transmit data has already been written to tdr during transmission of one-frame data, the sci3 transfers the written data to tsr to continue transmission. to achieve reliable serial transmission, write transmit data to tdr only once after confirming that the tdre bit in ssr is set to 1. tdr is initialized to h'ff at a reset and in standby, watch, or module standby mode. 10.3.5 serial mode register (smr) smr is used to set the sci3?s serial transfer format and select the on-chip baud rate generator clock source. smr is initialized to h'00 at a reset and in standby, watch, or module standby mode. bit bit name initial value r/w description 7 com 0 r/w communication mode 0: asynchronous mode 1: clocked synchronous mode 6 chr 0 r/w character length (enabled only in asynchronous mode) 0: selects 8 or 5 bits as the data length. 1: selects 7 or 5 bits as the data length. when 7-bit data is selected, the msb (bit 7) in tdr is not transmitted. to select 5 bits as the data length, set 1 to both the pe and mp bits. the three most significant bits (bits 7, 6, and 5) in tdr are not transmitted. in clocked synchronous mode, the data length is fixed to 8 bits regardless of the chr bit setting. 5 pe 0 r/w parity enable (enabled only in asynchronous mode) when this bit is set to 1, the parity bit is added to transmit data before transmission, and the parity bit is checked in reception. in clocked synchronous mode, parity bit addition and checking is not performed regardless of the pe bit setting.
rev. 4.00, 03/04, page 245 of 462 bit bit name initial value r/w description 4 pm 0 r/w parity mode (enabled only when the pe bit is 1 in asynchronous mode) 0: selects even parity. 1: selects odd parity. when even parity is selected, a parity bit is added in transmission so that the total number of 1 bits in the transmit data plus the parity bit is an even number; in reception, a check is carried out to confirm that the number of 1 bits in the receive data plus the parity bit is an even number. when odd parity is selected, a parity bit is added in transmission so that the total number of 1 bits in the transmit data plus the parity bit is an odd number; in reception, a check is carried out to confirm that the number of 1 bits in the receive data plus the parity bit is an odd number. if parity bit addition and checking is disabled in clocked synchronous mode and asynchronous mode, the pm bit setting is invalid. 3 stop 0 r/w stop bit length (enabled only in asynchronous mode) selects the stop bit length in transmission. 0:1stopbit 1:2stopbits for reception, only the first stop bit is checked, regardless of the value in the bit. if the second stop bit is 0, it is treated as the start bit of the next transmit character. 2 mp 0 r/w multiprocessor mode when this bit is set to 1, the multiprocessor communication function is enabled. the pe bit and pm bit settings are invalid. in clocked synchronous mode, this bit should be cleared to 0.
rev. 4.00, 03/04, page 246 of 462 bit bit name initial value r/w description 1 0 cks1 cks0 0 0 r/w r/w clock select 0 and 1 these bits select the clock source for the on-chip baud rate generator. 00: clock (n = 0) 01: w/2 or wclock(n=1) 10: /16 clock (n = 2) 11: /64 clock (n = 3) when the setting value is 01 in active mode and sleep mode, w/2 clock is set. in subactive mode and subsleep mode, w clock is set. the sci3 is enabled only when w /2 is selected for the cpu operating clock. for the relationship between the bit rate register setting and the baud rate, see section 10.3.8, bit rate register (brr). n is the decimal representation of the value of n in brr (see section 10.3.8, bit rate register (brr)). 10.3.6 serial control register 3 (scr3) scr3 is a register that enables or disables sci3 transfer operations and interrupt requests, and is also used to select the transfer clock source. scr3 is initialized to h'00 at a reset and in standby, watch, or module standby mode. for details on interrupt requests, refer to section 10.7, interrupts. bit bit name initial value r/w description 7 tie 0 r/w transmit interrupt enable when this bit is set to 1, the txi interrupt request is enabled. txi can be released by clearing the tdre bit or tie bit to 0. 6 rie 0 r/w receive interrupt enable when this bit is set to 1, rxi and eri interrupt requests are enabled. rxi and eri can be released by clearing bit rdrf or the fer, per, or oer error flag to 0, or by clearing bit rie to 0. 5 te 0 r/w transmit enable when this bit is set to 1, transmission is enabled. when thisbitis0,thetdrebitinssrisfixedat1.when transmit data is written to tdr while this bit is 1, bit tdre in ssr is cleared to 0 and serial data transmission is started. be sure to carry out smr settings, and setting of bit spc32 in spcr, to decide the transmission format before setting bit te to 1.
rev. 4.00, 03/04, page 247 of 462 bit bit name initial value r/w description 4 re 0 r/w receive enable when this bit is set to 1, reception is enabled. in this state, serial data reception is started when a start bit is detected in asynchronous mode or serial clock input is detected in clocked synchronous mode. be sure to carry out the smr settings to decide the reception format before setting bit re to 1. note that the rdrf, fer, per, and oer flags in ssr are not affected when bit re is cleared to 0, and retain their previous state. 3 mpie 0 r/w multiprocessor interrupt enable (enabled only when the mp bit in smr is 1 in asynchronous mode) when this bit is set to 1, receive data in which the multiprocessor bit is 0 is skipped, and setting of the rdrf, fer, and oer status flags in ssr is prohibited. on receiving data in which the multiprocessor bit is 1, this bit is automatically cleared and normal reception is resumed. for details, refer to section 10.6, multiprocessor communication function. 2 teie 0 r/w transmit end interrupt enable when this bit is set to 1, the tei interrupt request is enabled. tei can be released by clearing bit tdre to 0 and clearing bit tend to 0 in ssr, or by clearing bit teie to 0. 1 0 cke1 cke0 0 0 r/w r/w clock enable 0 and 1 selects the clock source. asynchronous mode: 00: internal baud rate generator 01: internal baud rate generator outputs a clock of the same frequency as the bit rate from the sck32 pin. 10: external clock inputs a clock with a frequency 16 times the bit rate from the sck32 pin. 11:reserved clocked synchronous mode: 00: internal clock (sck32 pin functions as clock output) 01:reserved 10: external clock (sck32 pin functions as clock input) 11:reserved
rev. 4.00, 03/04, page 248 of 462 10.3.7 serial status register (ssr) ssr is a register containing status flags of the sci3 and multiprocessor bits for transfer. 1 cannot be written to flags tdre, rdrf, oer, per, and fer; they can only be cleared. ssr is initialized to h'84 at a reset and in standby, watch, or module standby mode. bit bit name initial value r/w description 7 tdre 1 r/(w) * transmit data register empty indicates that transmit data is stored in tdr. [setting conditions] ? when the te bit in scr3 is 0 ? when data is transferred from tdr to tsr [clearing conditions] ? when 0 is written to tdre after reading tdre = 1 ? when the transmit data is written to tdr 6 rdrf 0 r/(w) * receivedataregisterfull indicates that the received data is stored in rdr. [setting condition] ? when serial reception ends normally and receive data is transferred from rsr to rdr [clearing conditions] ? when 0 is written to rdrf after reading rdrf = 1 ? when data is read from rdr if an error is detected in reception, or if the re bit in scr3 has been cleared to 0, rdr and bit rdrf are not affected and retain their previous state. note that if data reception is completed while bit rdrf is still set to 1, an overrun error (oer) will occur and the receive data will be lost.
rev. 4.00, 03/04, page 249 of 462 bit bit name initial value r/w description 5oer0 r/(w) * overrun error [setting condition] ? when an overrun error occurs in reception [clearing condition] ? when 0 is written to oer after reading oer = 1 when bit re in scr3 is cleared to 0, bit oer is not affected and retains its previous state. when an overrun error occurs, rdr retains the receive data it held before the overrun error occurred, and data received after the error is lost. reception cannot be continued with bit oer set to 1, and in clocked synchronous mode, transmission cannot be continued either. 4fer 0 r/(w) * framing error [setting condition] ? when a framing error occurs in reception [clearing condition] ? when 0 is written to fer after reading fer = 1 when bit re in scr3 is cleared to 0, bit fer is not affected and retains its previous state. note that, in 2-stop-bit mode, only the first stop bit is checked for a value of 1, and the second stop bit is not checked. when a framing error occurs, the receive data is transferred to rdr but bit rdrf is not set. reception cannot be continued with bit fer set to 1. in clocked synchronous mode, neither transmission nor reception is possible when bit fer is set to 1. 3 per 0 r/(w) * parity error [setting condition] ? when a parity error is generated during reception [clearing condition] ? when 0 is written to per after reading per = 1 when bit re in scr3 is cleared to 0, bit per is not affected and retains its previous state. receive data in which a parity error has occurred is still transferred to rdr, but bit rdrf is not set. reception cannot be continued with bit per set to 1. in clocked synchronous mode, neither transmission nor reception is possible when bit per is set to 1.
rev. 4.00, 03/04, page 250 of 462 bit bit name initial value r/w description 2 tend 1 r transmit end [setting conditions] ? when the te bit in scr3 is 0 ? when tdre = 1 at transmission of the last bit of a 1- byte serial transmit character [clearing conditions] ? when 0 is written to tdre after reading tdre = 1 ? when the transmit data is written to tdr 1 mpbr 0 r multiprocessor bit receive mpbr stores the multiprocessor bit in the receive character data. when the re bit in scr3 is cleared to 0, its previous state is retained. 0 mpbt 0 r/w multiprocessor bit transfer mpbt stores the multiprocessor bit to be added to the transmit character data. note: * only 0 can be written for clearing a flag. 10.3.8 bit rate register (brr) brr is an 8-bit readable/writable register that adjusts the bit rate. brr is initialized to h'ff at a reset and in standby, watch, or module standby mode. table 10.2 shows the relationship between the n setting in brr and the n setting in bits cks1 and cks0 of smr in asynchronous mode. table 10.4 shows the maximum bit rate for each frequency in asynchronous mode. the values shown in both tables 10.2 and 10.4 are values in active (high-speed) mode. table 10.5 shows the relationship between the n setting in brr and the n setting in bits cks1 and cks0 in smr in clocked synchronous mode. the values shown in table 10.5 are values in active (high-speed) mode. the n setting in brr and error for other operating frequencies and bit rates can be obtained by the following formulas: [asynchronous mode] n = osc 64 error (%) = 100 b (bit rate obtained from n, n, osc) ? r (bit rate in left-hand column in table 10.2) r (bit rate in left-hand column in table 10.2)
rev. 4.00, 03/04, page 251 of 462 [legend] b: bit rate (bit/s) n: brr setting for baud rate generator (0 n 255) osc: value of osc (hz) n: baud rate generator input clock number (n = 0, 2, or 3) (the relation between n and the clock is shown in table 10.3.) table 10.2 examples of brr settings for various bit rates (asynchronous mode) (1) osc 32.8 khz 38.4 khz 2 mhz 2.4576 mhz bit rate (bit/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 ? ? ? ? ? ? 2 17 ?1.36 2 21 ?0.83 150 ? ? ? 0 3 0 2 12 0.16 3 3 0 200 ? ? ? 0 2 0 2 9 ?2.34 3 2 0 250 0 1 2.5 ? ? ? 3 1 ?2.34 0 153 ?0.26 300 ? ? ? 0 1 0 0 103 0.16 3 1 0 600 ? ? ? 0 0 0 0 51 0.16 3 0 0 1200 ? ? ? 0 25 0.16 2 1 0 2400 0 12 0.16 2 0 0 4800 ? ? ? 0 7 0 9600 ? ? ? 0 3 0 19200 ? ? ? 0 1 0 31250 0 0 0 ? ? ? 38400 ? ? ? 0 0 0
rev. 4.00, 03/04, page 252 of 462 table 10.2 examples of brr settings for various bit rates (asynchronous mode) (2) osc 4mhz 10mhz 16mhz bit rate (bit/s) n n error (%) n n error (%) n n error (%) 110 3 8 ?1.36 3 21 0.88 3 35 ?1.36 150 2 25 0.16 3 15 1.73 3 25 0.16 200 3 4 ?2.34 3 11 1.73 3 19 ?2.34 250 2 15 ?2.34 3 9 ?2.34 3 15 ?2.34 300 2 12 0.16 3 7 1.73 3 12 0.16 600 0 103 0.16 3 3 1.73 2 25 0.16 1200 0 51 0.16 3 1 1.73 2 12 0.16 2400 0 25 0.16 3 0 1.73 0 103 0.16 4800 0 12 0.16 2 1 1.73 0 51 0.16 9600 ? ? ? 2 0 1.73 0 25 0.16 19200 ? ? ? 0 7 1.73 0 12 0.16 31250 0 1 0 0 4 0 0 7 0 38400 ? ? ? 0 3 1.73 ? ? ? [legend] no indication: setting not possible. ? : a setting is available but error occurs table 10.3 relation between n and clock smr setting n clock cks1 cks0 0 00 0 w /2 * 1 / w * 2 01 2 /16 1 0 3 /64 1 1 notes: 1. w /2 clock in active (medium-speed/high-speed) mode and sleep (medium-speed/high- speed) mode 2. w clock in subactive mode and subsleep mode in subactive or subsleep mode, the sci3 can be operated when cpu clock is w /2 only.
rev. 4.00, 03/04, page 253 of 462 table 10.4 maximum bit rate for each frequency (asynchronous mode) setting osc (mhz) maximum bit rate (bit/s) n n 0.0384 * 600 0 0 2 31250 0 0 2.4576 38400 0 0 4 62500 0 0 10 156250 0 0 16 250000 0 0 note: * when cks1 = 0 and cks0 = 1 in smr table 10.5 brr settings for various bit rates (clocked synchronous mode) (1) osc 38.4khz 2mhz 4mhz bit rate (bit/s) n n error (%) n n error (%) n n error (%) 200 0 23 0 ??? ??? 250 ? ? ? ? ? ? 2 124 0 300 2 0 0 ??? ??? 500 ??? ??? 1k 0 249 0 ? ? ? 2.5k 0 99 0 0 199 0 5k 0490 0990 10k 0240 0490 25k 090 0190 50k 040 090 100k ? ? ? 0 4 0 250k 0 0 0 0 1 0 500k 0 0 0 1m
rev. 4.00, 03/04, page 254 of 462 table 10.5 brr settings for various bit rates (clocked synchronous mode) (2) osc 10 mhz 16 mhz bit rate (bit/s) n n error (%) n n error (%) 200 ? ? ? ? ? ? 250 ? ? ? 3 124 0 300 ? ? ? ? ? ? 500 ? ? ? 2 249 0 1k ? ? ? 2 124 0 2.5k ? ? ? 2 49 0 5k 0 249 0 2 24 0 10k 0 124 0 0 199 0 25k 0 49 0 0 79 0 50k 0 24 0 0 39 0 100k ? ? ? 0 19 0 250k 0 4 0 0 7 0 500k ? ? ? 0 3 0 1m??? 0 1 0 [legend] blank : no setting is available. ? : a setting is available but error occurs. note: the value set in brr is given by the following formula: n = osc 8 2 2n b ? 1 b: bit rate (bit/s) n: brr setting for baud rate generator (0 n 255) osc: value of osc (hz) n: baud rate generator input clock number (n = 0, 2, or 3) (the relation between n and the clock is shown in table 10.6.)
rev. 4.00, 03/04, page 255 of 462 table 10.6 relation between n and clock smr setting n clock cks1 cks0 0 00 0 w /2 * 1 / w * 2 01 2 /16 1 0 3 /64 1 1 notes: 1. w /2 clock in active (medium-speed/high-speed) mode and sleep (medium-speed/high- speed) mode 2. w clock in subactive mode and subsleep mode in subactive or subsleep mode, the sci3 can be operated when cpu clock is w /2 only. 10.3.9 serial port control register (spcr) spcr selects whether input/output data of the rxd32 and txd32 pins is inverted or not. bit bit name initial value r/w description 7 6 ? ? 1 1 ? ? reserved these bits are always read as 1 and cannot be modified. 5 spc32 0 r/w p42/txd32 pin function switch selects whether pin p42/txd32 is used as p42 or as txd32. 0: p42 i/o pin 1: txd32 output pin 4 ? 1 ? reserved this bit is always read as 1 and cannot be modified. 3 scinv3 0 r/w txd32 pin output data inversion switch selects whether output data of the txd32 pin is inverted or not. 0: output data of txd32 pin is not inverted. 1: output data of txd32 pin is inverted. 2 scinv2 0 r/w rxd32 pin input data inversion switch selects whether input data of the rxd32 pin is inverted or not. 0: input data of rxd32 pin is not inverted. 1: input data of rxd32 pin is inverted.
rev. 4.00, 03/04, page 256 of 462 bit bit name initial value r/w description 1 0 ? ? 1 1 ? ? reserved these bits are always read as 1 and cannot be modified. 10.4 operation in asynchronous mode figure 10.2 shows the general format for asynchronous serial communication. one frame consists of a start bit (low level), followed by data (in lsb-first order), a parity bit (high or low level), and finally stop bits (high level). in asynchronous mode, synchronization is performed at the falling edge of the start bit during reception. the data is sampled on the 8th pulse of a clock with a frequency 16 times the bit period, so that the transfer data is latched at the center of each bit. inside the sci3, the transmitter and receiver are independent units, enabling full duplex. both the transmitter and the receiver also have a double-buffered structure, so data can be read or written during transmission or reception, enabling continuous data transfer. table 10.7 shows the 16 data transfer formats that can be set in asynchronous mode. the format is selected by the settings in smr as shown in table 10.8. lsb start bit msb mark state stop bit transmit/receive data 1 serial data parity bit 1 bit 1 or 2 bits 5, 7, or 8 bits 1 bit, or none one unit of transfer data (character or frame) figure 10.2 data format in asynchronous communication
rev. 4.00, 03/04, page 257 of 462 10.4.1 clock either an internal clock generated by the on-chip baud rate generator or an external clock input at the sck32 pin can be selected as the sci3?s serial clock source, according to the setting of the com bit in smr and the cke0 and cke1 bits in scr3. for details on selection of the clock source, see table 10.9. when an external clock is input at the sck32 pin, the clock frequency should be 16 times the bit rate used. when the sci3 is operated on an internal clock, the clock can be output from the sck32 pin. the frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is in the middle of the transmit data, as shown in figure 10.3. 0 1 character (frame) d0 d1 d2 d3 d4 d5 d6 d7 0/1 11 clock serial data figure 10.3 relationship between output clock and transfer data phase (asynchronous mode) (example with 8-bit data, parity, two stop bits)
rev. 4.00, 03/04, page 258 of 462 table 10.7 data transfer formats (asynchronous mode) 1 start start start start start start start start start start start start 2345 8-bit data 8-bit data 8-bit data 8-bit data 5-bit data 5-bit data 7-bit data 7-bit data 7-bit data 7-bit data 7-bit data 7-bit data 6789 stop stop 10 stop stop 11 stop mpb stop mpb stop stop stop stop p stop p stop stop mpb stop 12 stop mpb stop stop stop smr chr pe mp stop 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1 1 1 1 1 1 1 1 1 1 1 0 1 0 0 0 1 0 11 start start 8-bit data 8-bit data p stop p stop stop start start 5-bit data 5-bit data stop p p stop stop serial data transfer format and frame length * : don't care [legend] start stop p mpb : start bit : stop bit : parity bit : multiprocessor bit
rev. 4.00, 03/04, page 259 of 462 table 10.8 smr settings and corresponding data transfer formats smr data transfer format bit 7 com bit 6 chr bit 2 mp bit 5 pe bit 3 stop mode data length multiprocessor bit parity bit stop bit length 01bit 0 1 no 2bits 01bit 0 1 1 8-bit data yes 2bits 01bit 0 1 no 2bits 01bit 1 0 1 1 7-bit data no yes 2bits 01bit 0 1 8-bit data yes 2bits 01bit 0 1 1 5-bit data no 2bits 01bit 0 1 7-bit data yes no 2bits 01bit 0 1 1 1 1 asynchronous mode 5-bit data no yes 2bits 1 * 0 ** clocked synchronous mode 8-bit data no no no * : don?t care
rev. 4.00, 03/04, page 260 of 462 table 10.9 smr and scr3 settings and clock source selection smr scr3 bit 7 bit 1 bit 0 transmit/receive clock com cke1 cke0 mode clock source sck32 pin function 0 i/o port (sck32 pin not used) 0 1 internal outputs clock with same frequency as bit rate 0 10 asynchronous mode external inputs clock with frequency 16 times bit rate 0 0 internal outputs serial clock 1 10 clocked synchronous mode external inputs serial clock 011 101 111 reserved (do not specify these combinations)
rev. 4.00, 03/04, page 261 of 462 10.4.2 sci3 initialization follow the flowchart as shown in figure 10.4 to initialize the sci3. when the te bit is cleared to 0, the tdre flag is set to 1. note that clearing the re bit to 0 does not initialize the contents of the rdrf, per, fer, and oer flags, or the contents of rdr. when the external clock is used in asynchronous mode, the clock must be supplied even during initialization. when the external clock is used in clocked synchronous mode, the clock must not be supplied during initialization. wait start initialization set data transfer format in smr [1] set cke1 and cke0 bits in scr3 no yes set value in brr clear te and re bits in scr3 to 0 [2] [3] set te and re bits in scr3 to 1, and set rie, tie, teie, and mpie bits. set spc32 bit in spcr to 1 [4] 1-bit interval elapsed? [1] set the clock selection in scr3. be sure to clear bits rie, tie, teie, and mpie, and bits te and re, to 0. when the clock output is selected in asynchronous mode, clock is output immediately after cke1 and cke0 settings are made. when the clock output is selected at reception in clocked synchronous mode, clock is output immediately after cke1, cke0, and re are set to 1. [2] set the data transfer format in smr. [3] write a value corresponding to the bit rate to brr. not necessary if an external clock is used. [4] wait at least one bit interval, then set the te bit or re bit in scr3 to 1. setting bits te and re enables the txd32 and rxd32 pins to be used. also set the rie, tie, teie, and mpie bits, depending on whether interrupts are required. in asynchronous mode, the bits are marked at transmission and idled at reception to wait for the start bit. figure 10.4 sample sci3 initialization flowchart
rev. 4.00, 03/04, page 262 of 462 10.4.3 data transmission figure 10.5 shows an example of operation for transmission in asynchronous mode. in transmission, the sci3 operates as described below. 1. the sci3 monitors the tdre flag in ssr. if the flag is cleared to 0, the sci3 recognizes that data has been written to tdr, and transfers the data from tdr to tsr. 2. after transferring data from tdr to tsr, the sci3 sets the tdre flag to 1 and starts transmission. if the tie bit is set to 1 at this time, a txi interrupt request is generated. continuous transmission is possible because the txi interrupt routine writes next transmit data to tdr before transmission of the current transmit data has been completed. 3. the sci3 checks the tdre flag at the timing for sending the stop bit. 4. if the tdre flag is 0, the data is transferred from tdr to tsr, the stop bit is sent, and then serial transmission of the next frame is started. 5. if the tdre flag is 1, the tend flag in ssr is set to 1, the stop bit is sent, and then the ?mark state? is entered, in which 1 is output. if the teie bit in scr3 is set to 1 at this time, a tei interrupt request is generated. 6. figure 10.6 shows a sample flowchart for transmission in asynchronous mode. 1 frame start bit start bit transmit data transmit data parity bit stop bit parity bit stop bit mark state 1 frame 0 1 d0 d1 d7 0/1 1 1 1 0 d0 d1 d7 0/1 serial data tdre tend lsi operation txi interrupt request generated tdre flag cleared to 0 user processing data written to tdr txi interrupt request generated tei interrupt request generated figure 10.5 example sci3 operation in transmission in asynchronous mode (8-bit data, parity, one stop bit)
rev. 4.00, 03/04, page 263 of 462 no yes start transmission read tdre flag in ssr set spc32 bit in spcr to 1 [1] write transmit data to tdr yes no no yes read tend flag in ssr [2] no yes [3] clear pdr to 0 and set pcr to 1 clear te bit in scr3 to 0 tdre = 1 all data transmitted? tend = 1 break output? [1] read ssr and check that the tdre flag is set to 1, then write transmit data to tdr. when data is written to tdr, the tdre flag is automaticaly cleared to 0. (after the te bit is set to 1, one frame of 1 is output, then transmission is possible.) [2] to continue serial transmission, read 1 from the tdre flag to confirm that writing is possible, then write data to tdr. when data is written to tdr, the tdre flag is automaticaly cleared to 0. [3] to output a break in serial transmission, after setting pcr to 1 and pdr to 0, clear the te bit in scr3 to 0. figure 10.6 sample serial transmission flowchart (asynchronous mode)
rev. 4.00, 03/04, page 264 of 462 10.4.4 serial data reception figure 10.7 shows an example of operation for reception in asynchronous mode. in serial reception, the sci operates as described below. 1. the sci3 monitors the communication line. if a start bit is detected, the sci3 performs internal synchronization, receives data in rsr, and checks the parity bit and stop bit. ? parity check the sci3 checks that the number of 1 bits in the receive data conforms to the parity (odd or even) set in bit pm in the serial mode register (smr). ? stop bit check the sci3 checks that the stop bit is 1. if two stop bits are used, only the first is checked. ? status check the sci3 checks that bit rdrf is set to 0, indicating that the receive data can be transferred from rsr to rdr. 2. if an overrun error occurs (when reception of the next data is completed while the rdrf flag is still set to 1), the oer bit in ssr is set to 1. if the rie bit in scr3 is set to 1 at this time, an eri interrupt request is generated. receive data is not transferred to rdr. 3. if a parity error is detected, the per bit in ssr is set to 1 and receive data is transferred to rdr. if the rie bit in scr3 is set to 1 at this time, an eri interrupt request is generated. 4. if a framing error is detected (when the stop bit is 0), the fer bit in ssr is set to 1 and receive data is transferred to rdr. if the rie bit in scr3 is set to 1 at this time, an eri interrupt request is generated. 5. if reception is completed successfully, the rdrf bit in ssr is set to 1, and receive data is transferred to rdr. if the rie bit in scr3 is set to 1 at this time, an rxi interrupt request is generated. continuous reception is possible because the rxi interrupt routine reads the receive data transferred to rdr before reception of the next receive data has been completed.
rev. 4.00, 03/04, page 265 of 462 1 frame start bit start bit receive data receive data parity bit stop bit parity bit stop bit mark state (idle state) 1 frame 0 1 d0 d1 d7 0/1 1 0 1 0 d0 d1 d7 0/1 serial data rdrf fer lsi operation user processing rdrf cleared to 0 rdr data read framing error processing rxi request 0 stop bit detected eri request in response to framing error figure 10.7 example sci3 operation in reception in asynchronous mode (8-bit data, parity, one stop bit) table 10.10 shows the states of the ssr status flags and receive data handling when a receive error is detected. if a receive error is detected, the rdrf flag retains its state before receiving data. reception cannot be resumed while a receive error flag is set to 1. accordingly, clear the oer, fer, per, and rdrf bits to 0 before resuming reception. figure 10.8 shows a sample flowchart for serial data reception. table 10.10 ssr status flags and receive data handling ssr status flag rdrf * oer fer per receive data receive error type 1 1 0 0 lost overrun error 0 0 1 0 transferred to rdr framing error 0 0 0 1 transferred to rdr parity error 1 1 1 0 lost overrun error + framing error 1 1 0 1 lost overrun error + parity error 0 0 1 1 transferred to rdr framing error + parity error 1 1 1 1 lost overrun error + framing error + parity error note: * the rdrf flag retains the state it had before data reception. however, note that if rdr is read after an overrun error has occurred in a frame because reading of the receive data in the previous frame was delayed, the rdrf flag will be cleared to 0.
rev. 4.00, 03/04, page 266 of 462 yes no start reception [1] no yes read rdrf flag in ssr [2] [3] clear re bit in scr3 to 0 read oer, per, and fer flags in ssr error processing (continued on next page) [4] read receive data in rdr yes no oer+per+fer = 1 rdrf = 1 all data received? [1] read the oer, per, and fer flags in ssr to identify the error. if a receive error occurs, performs the appropriate error processing. [2] read ssr and check that rdrf = 1, then read the receive data in rdr. the rdrf flag is cleared automatically. [3] to continue serial reception, before the stop bit for the current frame is received, read the rdrf flag and read rdr. the rdrf flag is cleared automatically. [4] if a receive error occurs, read the oer, per, and fer flags in ssr to identify the error. after performing the appropriate error processing, ensure that the oer, per, and fer flags are all cleared to 0. reception cannot be resumed if any of these flags are set to 1. in the case of a framing error, a break can be detected by reading the value of the input port corresponding to the rxd32 pin. (a) figure 10.8 sample serial data reception flowchart (asynchronous mode) (1)
rev. 4.00, 03/04, page 267 of 462 (a) error processing parity error processing yes no clear oer, per, and fer flags in ssr to 0 no yes no yes framing error processing no yes overrun error processing oer = 1 fer = 1 break? per = 1 [4] figure 10.8 sample serial data reception flowchart (asynchronous mode) (2)
rev. 4.00, 03/04, page 268 of 462 10.5 operation in clocked synchronous mode figure 10.9 shows the general format for clocked synchronous communication. in clocked synchronous mode, data is transmitted or received synchronous with clock pulses. a single character in the transmit data consists of the 8-bit data starting from the lsb. in clocked synchronous serial communication, data on the transmission line is output from one falling edge of the serial clock to the next. in clocked synchronous mode, the sci3 receives data in synchronous with the rising edge of the serial clock. after 8-bit data is output, the transmission line holds the msb state. in clocked synchronous mode, no parity or multiprocessor bit is added. inside the sci3, the transmitter and receiver are independent units, enabling full-duplex communication through the use of a common clock. both the transmitter and the receiver also have a double- buffered structure, so data can be read or written during transmission or reception, enabling continuous data transfer. don ? t care don ? t care one unit of transfer data (character or frame) 8-bit bit 0 serial data synchronization clock bit 1 bit 3 bit 4 bit 5 lsb msb bit 2 bit 6 bit 7 * * note: * high except in continuous transfer figure 10.9 data format in clocked synchronous communication 10.5.1 clock either an internal clock generated by the on-chip baud rate generator or an external synchronization clock input at the sck32 pin can be selected, according to the setting of the com bit in smr and cke0 and cke1 bits in scr3. when the sci3 is operated on an internal clock, the serial clock is output from the sck32 pin. eight serial clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high. 10.5.2 sci3 initialization before transmitting and receiving data, the sci3 should be initialized as described in a sample flowchart in figure 10.4.
rev. 4.00, 03/04, page 269 of 462 10.5.3 serial data transmission figure 10.10 shows an example of sci3 operation for transmission in clocked synchronous mode. in serial transmission, the sci3 operates as described below. 1. the sci3 monitors the tdre flag in ssr, and if the flag is 0, the sci recognizes that data has been written to tdr, and transfers the data from tdr to tsr. 2. the sci3 sets the tdre flag to 1 and starts transmission. if the tie bit in scr3 is set to 1 at this time, a transmit data empty interrupt (txi) is generated. 3. 8-bit data is sent from the txd32 pin synchronized with the output clock when output clock mode has been specified, and synchronized with the input clock when use of an external clock has been specified. serial data is transmitted sequentially from the lsb (bit 0), from the txd32 pin. 4. the sci checks the tdre flag at the timing for sending the msb (bit 7). 5. if the tdre flag is cleared to 0, data is transferred from tdr to tsr, and serial transmission of the next frame is started. 6. if the tdre flag is set to 1, the tend flag in ssr is set to 1, and the tdre flag maintains the output state of the last bit. if the teie bit in scr3 is set to 1 at this time, a tei interrupt request is generated. 7. the sck32 pin is fixed high. figure 10.11 shows a sample flowchart for serial data transmission. even if the tdre flag is cleared to 0, transmission will not start while a receive error flag (oer, fer, or per) is set to 1. make sure that the receive error flags are cleared to 0 before starting transmission. serial clock serial data bit 1 bit 0 bit 7 bit 0 1 frame 1 frame bit 1 bit 6 bit 7 tdre tend lsi operation user processing txi interrupt request generated data written to tdr tdre flag cleared to 0 txi interrupt request generated tei interrupt request generated figure 10.10 example of sci3 operation in transmission in clocked synchronous mode
rev. 4.00, 03/04, page 270 of 462 no yes start transmission read tdre flag in ssr set spc32 bit in spcr to 1 [1] write transmit data to tdr no yes no yes read tend flag in ssr [2] clear te bit in scr3 to 0 tdre = 1 all data transmitted? tend = 1 [1] read ssr and check that the tdre flag is set to 1, then write transmit data to tdr. when data is written to tdr, the tdre flag is automatically cleared to 0. when clock output is selected and data is written to tdr, clocks are output to start the data transmission. [2] to continue serial transmission, be sure to read 1 from the tdre flag to confirm that writing is possible, then write data to tdr. when data is written to tdr, the tdre flag is automatically cleared to 0. figure 10.11 sample serial transmission flowchart (clocked synchronous mode)
rev. 4.00, 03/04, page 271 of 462 10.5.4 serial data reception (clocked synchronous mode) figure 10.12 shows an example of sci3 operation for reception in clocked synchronous mode. in serial reception, the sci3 operates as described below. 1. the sci3 performs internal initialization synchronous with a synchronous clock input or output, starts receiving data. 2. the sci3 stores the received data in rsr. 3. if an overrun error occurs (when reception of the next data is completed while the rdrf flag in ssr is still set to 1), the oer bit in ssr is set to 1. if the rie bit in scr3 is set to 1 at this time, an eri interrupt request is generated, receive data is not transferred to rdr, and the rdrf flag remains to be set to 1. 4. if reception is completed successfully, the rdrf bit in ssr is set to 1, and receive data is transferred to rdr. if the rie bit in scr3 is set to 1 at this time, an rxi interrupt request is generated. serial clock serial data 1 frame 1 frame bit 0 bit 7 bit 7 bit 0 bit 1 bit 6 bit 7 rdrf oer lsi operation user processing rxi interrupt request generated rdr data read rdrf flag cleared to 0 rxi interrupt request generated eri interrupt request generated by overrun error overrun error processing rdr data has not been read (rdrf = 1) figure 10.12 example of sci3 reception operation in clocked synchronous mode reception cannot be resumed while a receive error flag is set to 1. accordingly, clear the oer, fer, per, and rdrf bits to 0 before resuming reception. figure 10.13 shows a sample flowchart for serial data reception.
rev. 4.00, 03/04, page 272 of 462 yes no start reception [1] [4] no yes read rdrf flag in ssr [2] [3] clear re bit in scr3 to 0 error processing (continued below) read receive data in rdr yes no oer = 1 rdrf = 1 all data received? read oer flag in ssr error processing overrun error processing clear oer flag in ssr to 0 [4] [1] read the oer flag in ssr to determine if there is an error. if an overrun error has occurred, execute overrun error processing. [2] read ssr and check that the rdrf flag is set to 1, then read the receive data in rdr. when data is read from rdr, the rdrf flag is automatically cleared to 0. [3] to continue serial reception, before the msb (bit 7) of the current frame is received, reading the rdrf flag and reading rdr should be finished. when data is read from rdr, the rdrf flag is automatically cleared to 0. [4] if an overrun error occurs, read the oer flag in ssr, and after performing the appropriate error processing, clear the oer flag to 0. reception cannot be resumed if the oer flag is set to 1. figure 10.13 sample serial reception flowchart (clocked synchronous mode)
rev. 4.00, 03/04, page 273 of 462 10.5.5 simultaneous serial data transmission and reception figure 10.14 shows a sample flowchart for simultaneous serial transmit and receive operations. the following procedure should be used for simultaneous serial data transmit and receive operations. to switch from transmit mode to simultaneous transmit and receive mode, after checking that the sci3 has finished transmission and the tdre and tend flags are set to 1, clear te to 0. then simultaneously set te and re to 1 with a single instruction. to switch from receive mode to simultaneous transmit and receive mode, after checking that the sci3 has finished reception, clear re to 0. then after checking that the rdrf and receive error flags (oer, fer, and per) are cleared to 0, simultaneously set te and re to 1 with a single instruction. yes no start transmission/reception [3] error processing [4] read receive data in rdr yes no oer = 1 all data received? [1] read tdre flag in ssr set spc32 bit in spcr to 1 no yes tdre = 1 write transmit data to tdr no yes rdrf = 1 read oer flag in ssr [2] read rdrf flag in ssr clear te and re bits in scr to 0 [1] read ssr and check that the tdre flag is set to 1, then write transmit data to tdr. when data is written to tdr, the tdre flag is automatically cleared to 0. [2] read ssr and check that the rdrf flag is set to 1, then read the receive data in rdr. when data is read from rdr, the rdrf flag is automatically cleared to 0. [3] to continue serial transmission/ reception, before the msb (bit 7) of the current frame is received, finish reading the rdrf flag, reading rdr. also, before the msb (bit 7) of the current frame is transmitted, read 1 from the tdre flag to confirm that writing is possible. then write data to tdr. when data is written to tdr, the tdre flag is automatically cleared to 0. when data is read from rdr, the rdrf flag is automatically cleared to 0. [4] if an overrun error occurs, read the oer flag in ssr, and after performing the appropriate error processing, clear the oer flag to 0. transmission/reception cannot be resumed if the oer flag is set to 1. for overrun error processing, see figure 10.13. figure 10.14 sample flowchart of simultaneous serial transmit and receive operations (clocked synchronous mode)
rev. 4.00, 03/04, page 274 of 462 10.6 multiprocessor communication function use of the multiprocessor communication function enables data transfer between a number of processors sharing communication lines by asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. when multiprocessor communication is performed, each receiving station is addressed by a unique id code. the serial communication cycle consists of two component cycles; an id transmission cycle that specifies the receiving station, and a data transmission cycle. the multiprocessor bit is used to differentiate between the id transmission cycle and the data transmission cycle. if the multiprocessor bit is 1, the cycle is an id transmission cycle; if the multiprocessor bit is 0, the cycle is a data transmission cycle. figure 10.15 shows an example of inter-processor communication using the multiprocessor format. the transmitting station first sends the id code of the receiving station with which it wants to perform serial communication as data with a 1 multiprocessor bit added. it then sends transmit data as data with a 0 multiprocessor bit added. when data with a 1 multiprocessor bit is received, the receiving station compares that data with its own id. the station whose id matches then receives the data sent next. stations whose ids do not match continue to skip data until data with a 1 multiprocessor bit is again received. the sci3 uses the mpie bit in scr3 to implement this function. when the mpie bit is set to 1, transfer of receive data from rsr to rdr, error flag detection, and setting the ssr status flags, rdrf, fer, and oer to 1, are inhibited until data with a 1 multiprocessor bit is received. on reception of a receive character with a 1 multiprocessor bit, the mpbr bit in ssr is set to 1 and the mpie bit is automatically cleared, thus normal reception is resumed. if the rie bit in scr3 is set to 1 at this time, an rxi interrupt is generated. when the multiprocessor format is selected, the parity bit setting is rendered invalid. all other bit settings are the same as those in normal asynchronous mode. the clock used for multiprocessor communication is the same as that in normal asynchronous mode.
rev. 4.00, 03/04, page 275 of 462 transmitting station receiving station a receiving station b receiving station c receiving station d (id = 01) (id = 02) (id = 03) (id = 04) serial transmission line serial data id transmission cycle = receiving station specification data transmission cycle = data transmission to receiving station specified by id (mpb = 1) (mpb = 0) h'01 h'aa [legend] mpb: multiprocessor bit figure 10.15 example of communication using multiprocessor format (transmission of data h?aa to receiving station a)
rev. 4.00, 03/04, page 276 of 462 10.6.1 multiprocessor serial data transmission figure 10.16 shows a sample flowchart for multiprocessor serial data transmission. for an id transmission cycle, set the mpbt bit in ssr to 1 before transmission. for a data transmission cycle, clear the mpbt bit in ssr to 0 before transmission. all other sci3 operations are the same as those in asynchronous mode. no yes start transmission read tdre flag in ssr set spc32 bit in spcr to 1 [1] set mpbt bit in ssr yes no no yes read tend flag in ssr [2] no yes [3] clear pdr to 0 and set pcr to 1 clear te bit in scr3 to 0 tdre = 1 all data transmitted? tend = 1 break output? write transmit data to tdr [1] read ssr and check that the tdre flag is set to 1, set the mpbt bit in ssr to 0 or 1, then write transmit data to tdr. when data is written to tdr, the tdre flag is automatically cleared to 0. [2] to continue serial transmission, be sure to read 1 from the tdre flag to confirm that writing is possible, then write data to tdr. when data is written to tdr, the tdre flag is automatically cleared to 0. [3] to output a break in serial transmission, set the port pcr to 1, clear pdr to 0, then clear the te bit in scr3 to 0. figure 10.16 sample multiprocessor serial transmission flowchart
rev. 4.00, 03/04, page 277 of 462 10.6.2 multiprocessor serial data reception figure 10.17 shows a sample flowchart for multiprocessor serial data reception. if the mpie bit in scr3 is set to 1, data is skipped until data with a 1 multiprocessor bit is received. on receiving data with a 1 multiprocessor bit, the receive data is transferred to rdr. an rxi interrupt request is generated at this time. all other sci3 operations are the same as in asynchronous mode. figure 10.18 shows an example of sci3 operation for multiprocessor format reception. yes no start reception no yes [4] clear re bit in scr3 to 0 error processing (continued on next page) [5] yes no fer+oer = 1 rdrf = 1 all data received? set mpie bit in scr3 to 1 [1] [2] read oer and fer flags in ssr read rdrf flag in ssr [3] read receive data in rdr no yes [a] this station?s id? read oer and fer flags in ssr yes no read rdrf flag in ssr no yes fer+oer = 1 read receive data in rdr rdrf = 1 [1] set the mpie bit in scr3 to 1. [2] read oer and fer in ssr to check for errors. receive error processing is performed in cases where a receive error occurs. [3] read ssr and check that the rdrf flag is set to 1, then read the receive data in rdr and compare it with this station?s id. if the data is not this station?s id, set the mpie bit to 1 again. when data is read from rdr, the rdrf flag is automatically cleared to 0. [4] read ssr and check that the rdrf flag is set to 1, then read the data in rdr. [5] if a receive error occurs, read the oer and fer flags in ssr to identify the error. after performing the appropriate error processing, ensure that the oer and fer flags are all cleared to 0. reception cannot be resumed if either of these flags is set to 1. in the case of a framing error, a break can be detected by reading the rxd32 pin value. figure 10.17 sample multiprocessor serial reception flowchart (1)
rev. 4.00, 03/04, page 278 of 462 error processing yes no clear oer, and fer flags in ssr to 0 no yes no yes framing error processing overrun error processing oer = 1 fer = 1 break? [5] [a] figure 10.17 sample multiprocessor serial reception flowchart (2)
rev. 4.00, 03/04, page 279 of 462 1 frame start bit start bit receive data (id1) receive data (data1) mpb mpb stop bit stop bit mark state (idle state) 1 frame 0 1d0d1d711 11 0d0d1 d7 id1 0 serial data mpie rdrf rdr value rdr value lsi operation rxi interrupt request mpie cleared to 0 user processing rdrf flag cleared to 0 rxi interrupt request is not generated, and rdr retains its state rdr data read when data is not this station's id, mpie is set to 1 again 1 frame start bit start bit receive data (id2) receive data (data2) mpb mpb stop bit stop bit mark state (idle state) 1 frame 0 1d0d1d711 11 0 (a) when data does not match this receiver's id (b) when data matches this receiver's id d0 d1 d7 id2 data2 id1 0 serial data mpie rdrf lsi operation rxi interrupt request mpie cleared to 0 user processing rdrf flag cleared to 0 rxi interrupt request rdrf flag cleared to 0 rdr data read when data is this station's id, reception is continued rdr data read mpie set to 1 again figure 10.18 example of sci3 operation in reception using multiprocessor format (example with 8-bit data, multiprocessor bit, one stop bit)
rev. 4.00, 03/04, page 280 of 462 10.7 interrupts the sci3 creates the following six interrupt requests: transmission end, transmit data empty, receive data full, and receive errors (overrun error, framing error, and parity error). table 10.11 shows the interrupt sources. table 10.11 sci3 interrupt requests interrupt requests abbreviation interrupt sources receive data full rxi setting rdrf in ssr transmit data empty txi setting tdre in ssr transmission end tei setting tend in ssr receive error eri setting oer, fer, and per in ssr each interrupt request can be enabled or disabled by means of bits tie and rie in scr3. when bit tdre is set to 1 in ssr, a txi interrupt is requested. when bit tend is set to 1 in ssr, a tei interrupt is requested. these two interrupts are generated during transmission. the initial value of the tdre flag in ssr is 1. thus, when the tie bit in scr3 is set to 1 before transferring the transmit data to tdr, a txi interrupt request is generated even if the transmit data is not ready. the initial value of the tend flag in ssr is 1. thus, when the teie bit in scr3 is set to 1 before transferring the transmit data to tdr, a tei interrupt request is generated even if the transmit data has not been sent. it is possible to make use of the most of these interrupt requests efficiently by transferring the transmit data to tdr in the interrupt routine. to prevent the generation of these interrupt requests (txi and tei), set the enable bits (tie and teie) that correspond to these interrupt requests to 1, after transferring the transmit data to tdr. when bit rdrf is set to 1 in ssr, an rxi interrupt is requested, and if any of bits oer, per, and fer is set to 1, an eri interrupt is requested. these two interrupt requests are generated during reception. for further details, see section 3, exception handling. the sci3 can carry out continuous reception using rxi and continuous transmission using txi. these interrupts are shown in table 10.12.
rev. 4.00, 03/04, page 281 of 462 table 10.12 transmit/receive interrupts interrupt flags interrupt request conditions notes rxi rdrf rie when serial reception is performed normally and receive data is transferred from rsr to rdr, bit rdrf is set to 1, and if bit rie is set to 1 at this time, rxi is enabled and an interrupt is requested. (see figure 10.19(a).) the rxi interrupt routine reads the receive data transferred to rdr and clears bit rdrf to 0. continuous reception can be performed by repeating the above operations until reception of the next rsr data is completed. txi tdre tie whentsrisfoundtobeempty(on completion of the previous transmission) and the transmit data placed in tdr is transferred to tsr, bittdreissetto1.ifbittieissetto 1 at this time, txi is enabled and an interrupt is requested. (see figure 10.19(b).) the txi interrupt routine writes the next transmit data to tdr and clears bit tdre to 0. continuous transmission can be performed by repeating the above operations until the data transferred to tsr has been transmitted. tei tend teie when the last bit of the character in tsr is transmitted, if bit tdre is set to 1, bit tend is set to 1. if bit teie is set to 1 at this time, tei is enabled and an interrupt is requested. (see figure 10.19(c).) tei indicates that the next transmit data has not been written to tdr when the last bit of the transmit character in tsr is transmitted. rdr figure 10.19(a) rdrf setting and rxi interrupt
rev. 4.00, 03/04, page 282 of 462 tdr (next transmit data) tsr (transmission in progress) tdre = 0 txd32 pin tdr tsr figure 10.19(b) tdre setting and txi interrupt tdr tsr (transmission in progress) tend = 0 txd32 pin tdr tsr (transmission completed) tend 1 (tei request when teie = 1) txd32 pin figure 10.19(c) tend setting and tei interrupt 10.8 usage notes 10.8.1 break detection and processing when framing error detection is performed, a break can be detected by reading the rxd32 pin value directly. in a break, the input from the rxd32 pin becomes all 0, setting the fer flag, and possibly the per flag. note that as the sci3 continues the receive operation after receiving a break, even if the fer flag is cleared to 0, it will be set to 1 again. 10.8.2 mark state and break sending when te is 0, the txd32 pin is used as an i/o port whose direction (input or output) and level are determined by pcr and pdr. this can be used to set the txd32 pin to mark state (high level) or send a break during serial data transmission. to maintain the communication line at mark state until te is set to 1, set both pcr and pdr to 1. as te is cleared to 0 at this point, the txd32 pin becomes an i/o port, and 1 is output from the txd32 pin. to send a break during serial transmission, first set pcr to 1 and pdr to 0, and then clear te to 0. when te is cleared to 0, the transmitter is initialized regardless of the current transmission state, the txd32 pin becomes an i/o port, and 0 is output from the txd32 pin.
rev. 4.00, 03/04, page 283 of 462 10.8.3 receive error flags and transmit operations (clocked synchronous mode only) transmission cannot be started when a receive error flag (oer, per, or fer) is set to 1, even if the tdre flag is cleared to 0. be sure to clear the receive error flags to 0 before starting transmission. note also that receive error flags cannot be cleared to 0 even if the re bit is cleared to 0. 10.8.4 receive data sampling timing and reception margin in asynchronous mode in asynchronous mode, the sci3 operates on a basic clock with a frequency of 16 times the transfer rate. in reception, the sci3 samples the falling edge of the start bit using the basic clock, and performs internal synchronization. receive data is latched internally at the rising edge of the 8th pulse of the basic clock as shown in figure 10.20. thus, the reception margin in asynchronous mode is given by formula (1) below. m = (0.5 ? ) ? ? (l ? 0.5) f 100(%) ? ? ? ? ? ? 1 2n d ? 0.5 n ... formula (1) where n : ratio of bit rate to clock (n = 16) d :clockduty(d=0.5to1.0) l : frame length (l = 9 to 12) f : absolute value of clock rate deviation assuming values of f (absolute value of clock rate deviation) = 0 and d (clock duty) = 0.5 in formula (1), the reception margin can be given by the formula. m={0.5?1/(2 16)} 100 [%] = 46.875% however, this is only the computed value, and a margin of 20% to 30% should be allowed for in system design.
rev. 4.00, 03/04, page 284 of 462 internal basic clock 16 clocks 8 clocks receive data (rxd32) synchronization sampling timing start bit d0 d1 data sampling timing 15 0 7 15 0 07 figure 10.20 receive data sampling timing in asynchronous mode 10.8.5 note on switching sck32 function if pin sck32 is used as a clock output pin by the sci3 in clocked synchronous mode and is then switched to a general input/output pin (a pin with a different function), the pin outputs a low level signal for half a system clock ( ) cycle immediately after it is switched. this can be prevented by either of the following methods according to the situation. a. when an sck32 function is switched from clock output to non clock-output when stopping data transfer, issue one instruction to clear bits te and re to 0 and to set bits cke1andcke0inscr3to1and0,respectively. in this case, bit com in smr should be left 1. the above prevents sck32 from being used as a general input/output pin. to avoid an intermediate level of voltage from being applied to sck32, the line connected to sck32 should be pulled up to the v cc level via a resistor, or supplied with output from an external device. b. when an sck32 function is switched from clock output to general input/output when stopping data transfer, (i) issue one instruction to clear bits te and re to 0 and to set bits cke1 and cke0 in scr3 to 1 and 0, respectively. (ii) clear bit com in smr to 0 (iii) clear bits cke1 and cke0 in scr3 to 0 note that special care is also needed here to avoid an intermediate level of voltage from being applied to sck32.
rev. 4.00, 03/04, page 285 of 462 10.8.6 relation between writing to tdr and bit tdre bit tdre in the serial status register (ssr) is a status flag that indicates that data for serial transmission has not been prepared in tdr. when data is written to tdr, bit tdre is cleared to 0 automatically. when the sci3 transfers data from tdr to tsr, bit tdre is set to 1. data can be written to tdr irrespective of the state of bit tdre, but if new data is written to tdr while bit tdre is cleared to 0, the data previously stored in tdr will be lost if it has not yet been transferred to tsr. accordingly, to ensure that serial transmission is performed dependably, you should first check that bit tdre is set to 1, then write the transmit data to tdr only once (not two or more times). 10.8.7 relation between rdr reading and bit rdrf in a receive operation, the sci3 continually checks the rdrf flag. if bit rdrf is cleared to 0 when reception of one frame ends, normal data reception is completed. if bit rdrf is set to 1, this indicates that an overrun error has occurred. when the contents of rdr are read, bit rdrf is cleared to 0 automatically. therefore, if rdr is read more than once, the second and subsequent read operations will be performed while bit rdrf is cleared to 0. note that, when an rdr read is performed while bit rdrf is cleared to 0, if the read operation coincides with completion of reception of a frame, the next frame of data may be read. this is shown in figure 10.21. frame 1 frame 2 frame 3 data 1 communication line rdrf rdr data 2 data 3 data 1 data 2 rdr read rdr read (a) data 1 is read at point (a) data 2 is read at point (b) (b) figure 10.21 relation between rdr read timing and data in this case, only a single rdr read operation (not two or more) should be performed after first checking that bit rdrf is set to 1. if two or more reads are performed, the data read the first time should be transferred to ram, etc., and the ram contents used. also, ensure that there is sufficient margin in an rdr read operation before reception of the next frame is completed. to be
rev. 4.00, 03/04, page 286 of 462 precise in terms of timing, the rdr read should be completed before bit 7 is transferred in clocked synchronous mode, or before the stop bit is transferred in asynchronous mode. 10.8.8 transmit and receive operations when making state transition make sure that transmit and receive operations have completely finished before carrying out state transition processing. 10.8.9 setting in subactive or subsleep mode in subactive or subsleep mode, the sci3 can operate only when the cpu clock is w /2. the sa1 bit in syscr2 should be set to 1. 10.8.10 oscillator use with serial communications interface 3 (h8/38104 group only) when implementing serial communications interface 3 on the h8/38104 group, the system clock oscillator must be used. the on-chip oscillator should not be used in this case. see section 4.3.4, on-chip oscillator selection method, for information on switching between the system clock oscillator and the on-chip oscillator.
pwm1000a_000020020900 rev. 4.00, 03/04, page 287 of 462 section 11 10-bit pwm this lsi has a two-channel 10-bit pwm. the pwm with a low-path filter connected can be used as a d/a converter. figure 11.1(1) shows a block diagram of the 10-bit pwm of the h8/3802 group and h8/38004 group. figure 11.1(2) shows a block diagram of the 10-bit pwm of the h8/38104 group. 11.1 features ? choice of four conversion periods a conversion period of 4096/ with a minimum modulation width of 4/ , a conversion period of 2048/ with a minimum modulation width of 2/ , a conversion period of 1024/ with a minimum modulation width of 1/ , or a conversion period of 512/ with a minimum modulation width of 1/2 can be selected. ? pulse division method for less ripple ? use of module standby mode enables this module to be placed in standby mode independently when not used. (for details, refer to section 5.4, module standby function.) ? on the h8/38104 group it is possible to select between two types of pwm output: pulse- division 10-bit pwm and event counter pwm (pwm incorporating aec). (the h8/3802 group and h8/38004 group can only produce 10-bit pwm output.) refer to section 9.4, asynchronous event counter, for information on event counter pwm. [legend] pwcr: pwm control register pwdrl: pwm data register l pwdru: pwm data register u pwm: pwm output pin internal data bus pwcr pwdrl pwdru pwm pwm waveform generator /4 /2 /8 figure 11.1(1) block diagram of 10-bit pwm (h8/3802 group, h8/38004 group)
rev. 4.00, 03/04, page 288 of 462 [legend] pwcr: pwm control register pwdrl: pwm data register l pwdru: pwm data register u pwm: pwm output pin iecpwm: event counter pwm (pwm incorporating aec) internal data bus pwcr pwdrl pwdru pwm (iecpwm) pwm waveform generator iecpwm /4 /2 /8 figure 11.1(2) block diagram of 10-bit pwm (h8/38104 group) 11.2 input/output pins table 11.1 shows the 10-bit pwm pin configuration. table 11.1 pin configuration name abbreviation i/o function 10-bit pwm square-wave output 1 pwm1 output channel 1: 10-bit pwm waveform output pin/event counter pwm output pin * 10-bit pwm square-wave output 2 pwm2 output channel 2: 10-bit pwm waveform output pin/event counter pwm output pin * note: * h8/38104 group only
rev. 4.00, 03/04, page 289 of 462 11.3 register descriptions the 10-bit pwm has the following registers. ? pwm control register (pwcr) ? pwm data register u (pwdru) ? pwm data register l (pwdrl) 11.3.1 pwm control register (pwcr) on the h8/3802 group and h8/38004 group, pwcr selects the conversion period. bit bit name initial value r/w description 7 6 5 4 3 2 ? ? ? ? ? ? 1 1 1 1 1 1 ? ? ? ? ? ? reserved these bits are always read as 1, and cannot be modified. 1 0 pwcr1 pwcr0 0 0 w w clock select 1, 0 00: the input clock is (t =1/ ) ? the conversion period is 512/ , with a minimum modulation width of 1/2 01: the input clock is /2 (t =2/ ) ? the conversion period is 1024/ ,witha minimum modulation width of 1/ 10: the input clock is /4 (t =4/ ) ? the conversion period is 2048/ ,witha minimum modulation width of 2/ 11: the input clock is /8 (t =8/ ) ? the conversion period is 4096/ ,witha minimum modulation width of 4/ [legend] t : period of pwm clock input
rev. 4.00, 03/04, page 290 of 462 selects the pwcr output format and the conversion period on the h8/38104 group. bit bit name initial value r/w description 7 6 5 4 3 ? ? ? ? ? 1 1 1 1 1 ? ? ? ? ? reserved this bit is reserved. it is always read as 1 and cannot be written to. 2 pwcr2 0 w output format select 0: 10-bit pwm 1: event counter pwm (pwm incorporating aec) 1 0 pwcr1 pwcr0 0 0 w w clock select 1, 0 00: the input clock is (t =1/ ) ? the conversion period is 512/ , with a minimum modulation width of 1/2 01: the input clock is /2 (t =2/ ) ? the conversion period is 1,024/ ,witha minimum modulation width of 1/ 10: the input clock is /4 (t =4/ ) ? the conversion period is 2,048/ ,witha minimum modulation width of 2/ 11: the input clock is /8 (t =8/ ) ? the conversion period is 4,096/ ,witha minimum modulation width of 4/ [legend] t : period of pwm clock input 11.3.2 pwm data registers u and l (pwdru, pwdrl) pwdru and pwdrl indicate high level width in one pwm waveform cycle. pwdru and pwdrl are 10-bit write-only registers, with the upper 2 bits assigned to pwdru and the lower 8 bits to pwdrl. when read, all bits are always read as 1. both pwdru and pwdrl are accessible only in bytes. note that the operation is not guaranteed if word access is performed. when 10-bit data is written in pwdru and pwdrl, the contents are latched in the pwm waveform generator and the pwm waveform generation data is updated. when writing the 10-bit data, the order is as follows: pwdrl to pwdru. pwdru and pwdrl are initialized to h'fc00.
rev. 4.00, 03/04, page 291 of 462 11.4 operation 11.4.1 operation when using the 10-bit pwm, set the registers in this sequence: 1. set the pwm2 and pwm1 bits in the port mode register 9 (pmr9) to set the p91/pwm2 pin and p90/pwm1 pin to function as a pwm output pin. 2. set the pwcr0 and pwcr1 bits in pwcr to select a conversion period of either. on the h8/38104 group, the output format is selected using the pwcr2 bit. refer to section 9.4, asynchronous event counter, for information on how to select event counter pwm (pwm incorporating aec), one of the two available output formats. 3. set the output waveform data in pwdru and pwdrl. be sure to write byte data first to pwdrl and then to pwdru. when the data is written in pwdru, the contents of these registers are latched in the pwm waveform generator, and the pwm waveform generation data is updated in synchronization with internal signals. one conversion period consists of four pulses, as shown in figure 11.2. the total high-level width during this period (t h ) corresponds to the data in pwdru and pwdrl. this relation can be expressed as follows: t h = (data value in pwdru and pwdrl + 4) t /2 where t is the period of pwm clock input: 1/ (pwcr1=0,pwcr0=0),2/ (pwcr1 = 0, pwcr0 = 1), 4/ (pwcr1 = 1, pwcr0 = 0), or 8/ (pwcr1 = 1, pwcr0 = 1). if the data value in pwdru and pwdrl is from h'fffc to h'ffff, the pwm output stays high. when the data value is h'fc3c, t h is calculated as follows: t h =64 t /2 = 32 t one conversion period t f1 t h1 t h2 t h3 t h4 t f2 t f3 t f4 t h = t h1 + t h2 + t h3 + t h4 t f1 = t f2 = t f3 = t f4 figure 11.2 waveform output by 10-bit pwm
rev. 4.00, 03/04, page 292 of 462 11.4.2 pwm operating states table 11.2 shows the pwm operating states. table 11.2 pwm operating states operating mode reset active sleep watch sub-active sub-sleep standby module standby pwcr reset functions functions retained retained retained retained retained pwdru reset functions functions retained retained retained retained retained pwdrl reset functions functions retained retained retained retained retained
adcms3aa_000020020900 rev. 4.00, 03/04, page 293 of 462 section 12 a/d converter this lsi includes a successive approximation type 10-bit a/d converter that allows up to four analog input channels to be selected. the block diagram of the a/d converter is shown in figure 12.1. 12.1 features ? 10-bit resolution ? four input channels ? conversion time: at least 12.4 s per channel (at 5 mhz operation)/7.8 s(at8mhz operation)* ? sample and hold function ? conversion start method ? software ? interrupt request ? an a/d conversion end interrupt request (adi) can be generated ? use of module standby mode enables this module to be placed in standby mode independently when not used. (for details, refer to section 5.4, module standby function.) note: * h8/38104 group only.
rev. 4.00, 03/04, page 294 of 462 multiplexer internal data bus reference voltage + - comparator av cc av ss control logic adsr amr adrrh adrrl irrad an0 an1 an2 an3 av cc [legend] amr adsr adrrh, l irrad : a/d mode register : a/d start register : a/d result registers h and l : a/d conversion end interrupt request flag av ss figure 12.1 block diagram of a/d converter
rev. 4.00, 03/04, page 295 of 462 12.2 input/output pins table 12.1 shows the input pins used by the a/d converter. table 12.1 pin configuration pin name abbreviation i/o function analog power supply pin avcc input power supply and reference voltage of analog part analog ground pin avss input ground and reference voltage of analog part analog input pin 0 an0 input analog input pin 1 an1 input analog input pin 2 an2 input analog input pin 3 an3 input analog input pins 12.3 register descriptions the a/d converter has the following registers. ? a/d result registers h and l (adrrh and adrrl) ? a/d mode register (amr) ? a/d start register (adsr) 12.3.1 a/d result registers h and l (adrrh and adrrl) adrrh and adrrl are 16-bit read-only registers that store the results of a/d conversion. the upper 8 bits of the data are stored in adrrh, and the lower 2 bits in adrrl. adrrh and adrrl can be read by the cpu at any time, but the adrrh and adrrl values during a/d conversion are undefined. after a/d conversion is completed, the conversion result is stored as 10-bit data, and this data is retained until the next conversion operation starts. the initial values of adrrh and adrrl are undefined.
rev. 4.00, 03/04, page 296 of 462 12.3.2 a/d mode register (amr) amr sets the a/d conversion time and analog input pins. bit bit name initial value r/w description 7 cks 0 r/w clock select sets the a/d conversion time. 0: conversion time = 62 states 1: conversion time = 31 states 6 ? 0r/wreserved only 0 can be written to this bit. 5 4 ? ? 1 1 ? ? reserved these bits are always read as 1 and cannot be modified. 3 2 1 0 ch3 ch2 ch1 ch0 0 0 0 0 r/w r/w r/w r/w channel select 3 to 0 selects the analog input channel. 00xx: no channel selected 0100: an0 0101: an1 0110: an2 1xxx: using prohibited the channel selection should be made while the adsf bit is cleared to 0. [legend] x: don't care. 12.3.3 a/d start register (adsr) adsr starts and stops the a/d conversion. bit bit name initial value r/w description 7 adsf 0 r/w when this bit is set to 1, a/d conversion is started. when conversion is completed, the converted data is set in adrrh and adrrl and at the same time this bit is cleared to 0. if this bit is written to 0, a/d conversion can be forcibly terminated. 6to0 ? all 1 ? reserved these bits are always read as 1 and cannot be modified.
rev. 4.00, 03/04, page 297 of 462 12.4 operation the a/d converter operates by successive approximation with 10-bit resolution. when changing the conversion time or analog input channel, in order to prevent incorrect operation, first clear the bitadsfto0inadsr. 12.4.1 a/d conversion 1. a/d conversion is started from the selected channel when the adsf bit in adsr is set to 1, according to software. 2. when a/d conversion is completed, the result is transferred to the a/d result register. 3. on completion of conversion, the irrad flag in irr2 is set to 1. if the ienad bit in ienr2 is set to 1 at this time, an a/d conversion end interrupt request is generated. 4. the adsf bit remains set to 1 during a/d conversion. when a/d conversion ends, the adsf bit is automatically cleared to 0 and the a/d converter enters the wait state. 12.4.2 operating states of a/d converter table 12.2 shows the operating states of the a/d converter. table 12.2 operating states of a/d converter operating mode reset active sleep watch sub-active sub-sleep standby module standby amr reset functions functions retained retained retained retained retained adsr reset functions functions reset reset reset reset reset adrrh retained * functions functions retained retained retained retained retained adrrl retained * functions functions retained retained retained retained retained note: * undefined in a power-on reset.
rev. 4.00, 03/04, page 298 of 462 12.5 example of use an example of how the a/d converter can be used is given below, using channel 1 (pin an1) as the analog input channel. figure 12.2 shows the operation timing. 1. bits ch3 to ch0 in the a/d mode register (amr) are set to 0101, making pin an1 the analog input channel. a/d interrupts are enabled by setting bit ienad to 1, and a/d conversion is started by setting bit adsf to 1. 2. when a/d conversion is completed, bit irrad is set to 1, and the a/d conversion result is stored in adrrh and adrrl. at the same time bit adsf is cleared to 0, and the a/d converter goes to the idle state. 3. bit ienad = 1, so an a/d conversion end interrupt is requested. 4. the a/d interrupt handling routine starts. 5. the a/d conversion result is read and processed. 6. the a/d interrupt handling routine ends. if bit adsf is set to 1 again afterward, a/d conversion starts and steps 2 through 6 take place. figures 12.3 and 12.4 show flowcharts of procedures for using the a/d converter.
rev. 4.00, 03/04, page 299 of 462 interrupt (irrad) ienad adsf adrrh adrrl channel 1 (an1) operating state note: * indicates instruction execution by software. set * set * a/d conversion starts idle idle idle a/d conversion (1) a/d conversion (2) set * a/d conversion result (1) read conversion result a/d conversion result (2) read conversion result figure 12.2 example of a/d conversion operation
rev. 4.00, 03/04, page 300 of 462 start set a/d conversion speed and input channel disable a/d conversion end interrupt start a/d conversion perform a/d conversion? end read adsr adsf = 0? read adrrh/adrrl data yes yes no no figure 12.3 flowchart of procedure for using a/d converter (polling by software) set a/d conversion speed and input channel start enable a/d conversion end interrupt start a/d conversion clear irrad bit in irr2 to 0 read adrrh/adrrl data a/d conversion end interrupt generated? perform a/d conversion? end no no yes yes figure 12.4 flowchart of procedure for using a/d converter (interrupts used)
rev. 4.00, 03/04, page 301 of 462 12.6 a/d conversion accuracy definitions this lsi's a/d conversion accuracy definitions are given below. ? resolution the number of a/d converter digital output codes ? quantization error the deviation inherent in the a/d converter, given by 1/2 lsb (see figure 12.5). ? offset error the deviation of the analog input voltage value from the ideal a/d conversion characteristic when the digital output changes from the minimum voltage value 0000000000 to 0000000001 (see figure 12.6). ? full-scale error the deviation of the analog input voltage value from the ideal a/d conversion characteristic when the digital output changes from 1111111110 to 1111111111 (see figure 12.6). ? nonlinearity error the error with respect to the ideal a/d conversion characteristics between zero voltage and full-scale voltage. does not include offset error, full-scale error, or quantization error. ? absolute accuracy the deviation between the digital value and the analog input value. includes offset error, full- scale error, quantization error, and nonlinearity error. 111 110 101 100 011 010 001 000 1 8 2 8 6 8 7 8 fs quantization error digital output ideal a/d conversion characteristic analog input voltage 3 8 4 8 5 8 figure 12.5 a/d conversion accuracy definitions (1)
rev. 4.00, 03/04, page 302 of 462 fs digital output ideal a/d conversion characteristic nonlinearity error analog input voltage offset error actual a/d conversion characteristic full-scale error figure 12.6 a/d conversion accuracy definitions (2) 12.7 usage notes 12.7.1 permissible signal source impedance this lsi's analog input is designed such that conversion accuracy is guaranteed for an input signal for which the signal source impedance is 10 k ? or less. this specification is provided to enable the a/d converter's sample-and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 10 k ? , charging may be insufficient and it may not be possible to guarantee a/d conversion accuracy. however, with a large capacitance provided externally, the input load will essentially comprise only the internal input resistance of 10 k ? ,and the signal source impedance is ignored. however, as a low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a large differential coefficient (e.g., 5 mv/ s or greater) (see figure 12.7). when converting a high-speed analog signal, a low- impedance buffer should be inserted. 12.7.2 influences on absolute accuracy adding capacitance results in coupling with gnd, and therefore noise in gnd may adversely affect absolute accuracy. be sure to make the connection to an electrically stable gnd. care is also required to ensure that filter circuits do not interfere with digital signals or act as antennas on the mounting board.
rev. 4.00, 03/04, page 303 of 462 20 pf 10 k ? c in = 15 pf sensor output impedance to 10 k ? this lsi low-pass filter c to 0.1 f sensor input a/d converter equivalent circuit figure 12.7 example of analog input circuit 12.7.3 usage notes 1. adrrh and adrrl should be read only when the adsf bit in adsr is cleared to 0. 2. changing the digital input signal at an adjacent pin during a/d conversion may adversely affect conversion accuracy. 3. when a/d conversion is started after clearing module standby mode, wait for 10 clock cycles before starting a/d conversion. 4. in active mode and sleep mode, the analog power supply current flows in the ladder resistance even when the a/d converter is on standby. therefore, if the a/d converter is not used, it is recommended that avcc be connected to the system power supply and the adckstp bit be cleared to 0 in ckstpr1.
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lcdsg02a_000020020900 rev. 4.00, 03/04, page 305 of 462 section 13 lcd controller/driver this lsi has an on-chip segment-type lcd control circuit, lcd driver, and power supply circuit, enabling it to directly drive an lcd panel. 13.1 features ? display capacity duty cycle internal driver static 25 seg 1/2 25 seg 1/3 25 seg 1/4 25 seg ? lcd ram capacity 8 bits 13 bytes (104 bits) ? word access to lcd ram the segment output pins can be used as ports. seg24 to seg1 pins can be used as ports in groups of four. ? common output pins not used because of the duty cycle can be used for common double- buffering (parallel connection). with1/2duty,parallelconnectionofcom1tocom2,andofcom3tocom4,canbeused in static mode, parallel connection of com1 to com2, com3, and com4 can be used ? choice of 11 frame frequencies ? a or b waveform selectable by software ? removal of split-resistance can be controlled in software. note that this capability is implemented in the h8/38104 group only. ? on-chip power supply split-resistance ? display possible in operating modes other than standby mode ? use of module standby mode enables this module to be placed in standby mode independently when not used. (for details, refer to section 5.4, module standby function.)
rev. 4.00, 03/04, page 306 of 462 figures 13.1(1) and 13.1(2) show a block diagram of the lcd controller/driver. /2 to /256 w segn lpcr lcr lcr2 display timing generator lcd ram 13 bytes internal data bus 25-bit shift register lcd drive power supply segment driver common data latch common driver v1 v2 v3 vss com1 com4 seg25 seg24 seg23 seg22 seg21 seg1 [legend] lpcr: lcd port control register lcr: lcd control register lcr2: lcd control register 2 vcc figure 13.1(1) block diagram of lcd controller/driver (h8/3802 group, h8/38004 group)
rev. 4.00, 03/04, page 307 of 462 /2 to /256 w segn lpcr lcr lcr2 display timing generator lcd ram 13 bytes internal data bus 25-bit shift register lcd drive power supply segment driver common data latch common driver v1 v2 v3 vss com1 com4 seg25 seg24 seg23 seg22 seg21 seg1 [legend] lpcr: lcd port control register lcr: lcd control register lcr2: lcd control register 2 vcc figure 13.1(2) block diagram of lcd controller/driver (h8/38104 group)
rev. 4.00, 03/04, page 308 of 462 13.2 input/output pins table 13.1 shows the lcd controller/driver pin configuration. table 13.1 pin configuration name abbreviation i/o function segment output pins seg25 to seg1 output lcd segment drive pins all pins are multiplexed as port pins (setting programmable) common output pins com4 to com1 output lcd common drive pins pinscanbeusedinparallelwithstaticor 1/2 duty lcd power supply pins v1, v2, v3 ? used when a bypass capacitor is connected externally, and when an external power supply circuit is used
rev. 4.00, 03/04, page 309 of 462 13.3 register descriptions the lcd controller/driver has the following registers. ? lcd port control register (lpcr) ? lcd control register (lcr) ? lcd control register 2 (lcr2) ? lcd ram 13.3.1 lcd port control register (lpcr) lpcr selects the duty cycle, lcd driver, and pin functions. bit bit name initial value r/w description 7 6 5 dts1 dts0 cmx 0 0 0 r/w r/w r/w duty cycle select 1 and 0 commonfunctionselect the combination of dts1 and dts0 selects static, 1/2, 1/3, or 1/4 duty. cmx specifies whether or not the same waveform is to be output from multiple pins to increase the common drive power when not all common pins are used because of the duty setting. for details, see table 13.2. 4? ? wreserved only 0 can be written to this bit. 3 2 1 0 sgs3 sgs2 sgs1 sgs0 0 0 0 0 r/w r/w r/w r/w segment driver select 3 to 0 select the segment drivers to be used. for details, see table 13.3.
rev. 4.00, 03/04, page 310 of 462 table 13.2 duty cycle and common function selection bit 7: dts1 bit 6: dts0 bit 5: cmx duty cycle common drivers notes 0 0 0 static com1 do not use com4, com3, and com2 1 com4 to com1 com4, com3, and com2 output the same waveform as com1 1 0 1/2 duty com2 to com1 do not use com4 and com3 1 com4 to com1 com4 outputs the same waveform as com3, and com2 outputs the same waveform as com1 1 0 0 1/3 duty com3 to com1 do not use com4 1 com4tocom1 donotusecom4 1 x 1/4duty com4tocom1 ? [legend] x: don?t care table 13.3 segment driver selection function of pins seg25 to seg1 bit 3: sgs3 bit 2: sgs2 bit 1: sgs1 bit 0: sgs0 seg25 seg24 to seg21 seg20 to seg17 seg16 to seg13 seg12 to seg9 seg8 to seg5 seg4 to seg1 0 0 0 0 port port port port port port port 1 port port port port port port seg 1 0 port port port port port seg seg 1 port port port port seg seg seg 1 0 0 port port port seg seg seg seg 1 port port seg seg seg seg seg 1 0 port seg seg seg seg seg seg 1 seg seg seg seg seg seg seg 1 0 0 0 seg seg seg seg seg seg seg 1 seg seg seg seg seg seg port 1 0 seg seg seg seg seg port port 1 seg seg seg seg port port port 1 0 0 seg seg seg port port port port 1 seg seg port port port port port 1 0 seg port port port port port port 1 port port port port port port port
rev. 4.00, 03/04, page 311 of 462 13.3.2 lcd control register (lcr) lcr controls lcd drive power supply and display data, and selects the frame frequency. bit bit name initial value r/w description 7? 1 ?reserved this bit is always read as 1 and cannot be modified. 6 psw 0 r/w lcd drive power supply control can be used to disconnect the lcd drive power supply from vcc when lcd display is not required in power- down mode, or when an external power supply is used. when the act bit is cleared to 0, and also in standby mode, the lcd drive power supply is disconnected from vcc regardless of the setting of this bit. 0: lcd drive power supply is disconnected from vcc 1: lcd drive power supply is connected to vcc 5 act 0 r/w display function activate specifies whether or not the lcd controller/driver is used. clearing this bit to 0 halts operation of the lcd controller/driver. the lcd drive power supply is also turned off, regardless of the setting of the psw bit. however, register contents are retained. 0: lcd controller/driver operation halted 1: lcd controller/driver operation enabled 4 disp 0 r/w display data control specifies whether the lcd ram contents are displayed or blank data is displayed regardless of the lcd ram contents. 0: blank data is displayed 1: lcd ram data is displayed 3 2 1 0 cks3 cks2 cks1 cks0 0 0 0 0 r/w r/w r/w r/w frame frequency select 3 to 0 select the operating clock and the frame frequency. in subactive mode, watch mode, and subsleep mode, the system clock ( ) is halted, and therefore display operations are not performed if one of the clocks from /2 to /256 is selected. if lcd display is required in these modes, w , w /2, or w /4 must be selected as the operating clock. for details, see table 13.4.
rev. 4.00, 03/04, page 312 of 462 table 13.4 frame frequency selection bit 3: bit 2: bit 1: bit 0: frame frequency * 1 cks3 cks2 cks1 cks0 operating clock =2mhz = 250 khz * 3 0x00 w 128 hz * 2 128 hz * 2 1 w /2 64 hz * 2 64 hz * 2 1x w /4 32 hz * 2 32 hz * 2 1000 /2 ? 244 hz 1 /4 977 hz 122 hz 10 /8 488 hz 61 hz 1 /16 244 hz 30.5 hz 100 /32 122 hz ? 1 /64 61 hz ? 10 /128 30.5 hz ? 1 /256 ? ? [legend] x: don?t care notes: 1. when 1/3 duty is selected, the frame frequency is 4/3 times the value shown. 2. this is the frame frequency when w = 32.768 khz. 3. this is the frame frequency in active (medium-speed, osc /16) mode when =2mhz.
rev. 4.00, 03/04, page 313 of 462 13.3.3 lcd control register 2 (lcr2) lcr2 controls switching between the a waveform and b waveform and removal of split- resistance. note that removal of split-resistance control is only implemented on the h8/38104 group. bit bit name initial value r/w description 7 lcdab 0 r/w a waveform/b waveform switching control bit 7 specifies whether the a waveform or b waveform is used as the lcd drive waveform. 0: drive using a waveform 1: drive using b waveform 6, 5 ? all 1 ? reserved these bits are always read as 1 and cannot be modified. 4? ? wreserved this bit is always read as 0. 3to0 * cds3 cds2 cds1 cds0 all 0 r/w removal of split-resistance control these bits control whether the split-resistance is removed or connected. cds3 = 0, cds2 = cds1 = cds0 = 1: split-resistance removed all other settings: split-resistance connected note: * applies to h8/38104 group only. on the h8/3802 group or h8/38004 group, these bits arereservedlikebit4.
rev. 4.00, 03/04, page 314 of 462 13.4 operation 13.4.1 settings up to lcd display to perform lcd display, the hardware and software related items described below must first be determined. 1. hardware settings a. using 1/2 duty when 1/2 duty is used, interconnect pins v2 and v3 as shown in figure 13.2. v1 v2 v3 v cc v ss figure 13.2 handling of lcd drive power supply when using 1/2 duty b. large-panel display as the impedance of the on-chip power supply split-resistance is large, it may not be suitable for driving a large panel. if the display lacks sharpness when using a large panel, refer to section 13.4.4, boosting lcd drive power supply. when static or 1/2 duty is selected, the common output drive capability can be increased. set cmx to 1 when selecting the duty cycle. in this mode, with a static duty cycle pins com4 to com1 output the same waveform, and with 1/2 duty the com1 waveform is output from pins com2 and com1, and the com2 waveform is output from pins com4 and com3. c. lcd drive power supply setting with this lsi, there are two ways of providing lcd power: by using the on-chip power supply circuit, or by using an external power supply circuit. when an external power supply circuit is used for the lcd drive power supply, connect the external power supply to the v1 pin. 2. software settings a. duty selection any of four duty cycles?static, 1/2 duty, 1/3 duty, or 1/4 duty?can be selected with bits dts1 and dts0.
rev. 4.00, 03/04, page 315 of 462 b. segment selection the segment drivers to be used can be selected with bits sgs3 to sgs0. c. frame frequency selection the frame frequency can be selected by setting bits cks3 to cks0. the frame frequency should be selected in accordance with the lcd panel specification. for the clock selection method in watch mode, subactive mode, and subsleep mode, see section 13.4.3, operation in power-down modes. d. a or b waveform selection either the a or b waveform can be selected as the lcd waveform to be used by means of lcdab. e. lcd drive power supply selection when an external power supply circuit is used, turn the lcd drive power supply off with the psw bit. 13.4.2 relationship between lcd ram and display the relationship between the lcd ram and the display segments differs according to the duty cycle. lcd ram maps for the different duty cycles are shown in figures 13.3 to 13.6. after setting the registers required for display, data is written to the part corresponding to the duty using the same kind of instruction as for ordinary ram, and display is started automatically when turned on. word- or byte-access instructions can be used for ram setting. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 h'f74c h'f740 seg25 seg25 seg25 seg25 seg2 seg2 seg2 seg2 seg1 seg1 seg1 seg1 com4 com3 com2 com1 com4 com3 com2 com1 figure 13.3 lcd ram map (1/4 duty)
rev. 4.00, 03/04, page 316 of 462 h'f74c h'f740 seg25 seg25 seg25 seg2 seg2 seg2 seg1 seg1 seg1 com3 space not used for display com2 com1 com3 com2 com1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 figure 13.4 lcd ram map (1/3 duty) h'f74c h'f740 h'f746 seg25 seg25 seg4 seg4 seg3 seg3 seg2 seg2 seg1 seg1 display space space not used for display com2 com1 com2 com1 com2 com1 com2 com1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 figure 13.5 lcd ram map (1/2 duty)
rev. 4.00, 03/04, page 317 of 462 h'f74c h'f740 h'f743 seg25 display space space not used for display seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 com1 com1 com1 com1 com1 com1 com1 com1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 figure 13.6 lcd ram map (static mode)
rev. 4.00, 03/04, page 318 of 462 m data (a) waveform with 1/4 duty (c) waveform with 1/2 duty (d) waveform with static output m: lcd alternation signal (b) waveform with 1/3 duty com1 com2 com3 com4 segn m data com1 com2 segn m data com1 segn m data 1 frame 1 frame 1 frame 1 frame com1 v1 v2 v3 vss v1 v2 v3 vss v1 v2 v3 vss v1 v2 v3 vss v1 v2 v3 vss v1 v2,v3 vss v1 vss v1 vss v1 v2,v3 vss v1 v2,v3 vss v1 v2 v3 vss v1 v2 v3 vss v1 v1 v2 v3 vss v2 v3 vss com2 com3 segn figure 13.7 output waveforms for each duty cycle (a waveform)
rev. 4.00, 03/04, page 319 of 462 m: lcd alternation signal m data (a) waveform with 1/4 duty (c) waveform with 1/2 duty (d) waveform with static output (b) waveform with 1/3 duty com1 com2 com3 com4 segn m data com1 com2 segn m data com1 segn m data 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame com1 v1 v2 v3 vss v1 v2 v3 vss v1 v2 v3 vss v1 v2 v3 vss v1 v2 v3 vss v1 v2,v3 vss v1 vss v1 vss v1 v2,v3 vss v1 v2,v3 vss v1 v2 v3 vss v1 v2 v3 vss v1 v1 v2 v3 vss v2 v3 vss com2 com3 segn figure 13.8 output waveforms for each duty cycle (b waveform)
rev. 4.00, 03/04, page 320 of 462 table 13.5 output levels data 0011 m 0101 static common output v1 vss v1 vss segment output v1 vss vss v1 1/2 duty common output v2, v3 v2, v3 v1 vss segment output v1 vss vss v1 1/3 duty common output v3 v2 v1 vss segment output v2 v3 vss v1 1/4 duty common output v3 v2 v1 vss segment output v2 v3 vss v1 m: lcd alternation signal 13.4.3 operation in power-down modes in this lsi, the lcd controller/driver can be operated even in the power-down modes. the operating state of the lcd controller/driver in the power-down modes is summarized in table 13.6. in subactive mode, watch mode, and subsleep mode, the system clock oscillator stops, and therefore, unless w , w /2, or w /4 has been selected by bits cks3 to cks0, the clock will not be supplied and display will halt. since there is a possibility that a direct current will be applied to the lcd panel in this case, it is essential to ensure that w , w /2, or w /4 is selected. in active (medium-speed) mode, the system clock is switched, and therefore bits cks3 to cks0 must be modified to ensure that the frame frequency does not change.
rev. 4.00, 03/04, page 321 of 462 table 13.6 power-down modes and display operation mode reset active sleep watch subactive subsleep standby module standby clock runs runs runs stops stops stops stops stops * 4 w runs runs runs runs runs runs stops * 1 stops * 4 display act = 0 stops stops stops stops stops stops stops * 2 stops operation act = 1 stops functions functions functions * 3 functions * 3 functions * 3 stops * 2 stops notes: 1. the subclock oscillator does not stop, but clock supply is halted. 2. the lcd drive power supply is turned off regardless of the setting of the psw bit. 3. display operation is performed only if w , w /2, or w /4 is selected as the operating clock. 4. the clock supplied to the lcd stops. 13.4.4 boosting lcd drive power supply when the on-chip power supply capacity is insufficient for the lcd panel drivability, the power- supply impedance must be reduced. this can be done by connecting bypass capacitors of around 0.1 to 0.3 f to pins v1 to v3, as shown in figure 13.9, or by adding a split-resistor externally. this lsi v cc v ss v1 v2 v3 r r r r r = c = 0.1 to 0.3 f several k ? to several m ? figure 13.9 connection of external split-resistance
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lvi0000a_000020030300 rev. 4.00, 03/04, page 323 of 462 section 14 power-on reset and low-voltage detection circuits (h8/38104 group only) this lsi can include a power-on reset circuit. the low-voltage detection circuit consists of two circuits: lvdi (interrupt by low voltage detect) and lvdr (reset by low voltage detect) circuits. this circuit is used to prevent abnormal operation (runaway execution) from occurring due to the power supply voltage fall and to recreate the state before the power supply voltage fall when the power supply voltage rises again. even if the power supply voltage falls, the unstable state when the power supply voltage falls below the guaranteed operating voltage can be removed by entering standby mode when exceeding the guaranteed operating voltage and during normal operation. thus, system stability can be improved. if the power supply voltage falls more, the reset state is automatically entered. if the power supply voltage rises again, the reset state is held for a specified period, then active mode is automatically entered. figure 14.1 is a block diagram of the power-on reset circuit and the low-voltage detection circuit. 14.1 features ? power-on reset circuit uses an external capacitor to generate an internal reset signal when power is first supplied. ? low-voltage detection circuit lvdr: monitors the power-supply voltage, and generates an internal reset signal when the voltage falls below a specified value. lvdi: monitors the power-supply voltage, and generates an interrupt when the voltage falls below or rises above respective specified values. two pairs of detection levels for reset generation voltage are available: when only the lvdr circuit is used, or when the lvdi and lvdr circuits are both used. in addition, power supply rise/drop detection voltages and a detection voltage reference voltage may be input from an external source, allowing the detection level to be set freely by the user.
rev. 4.00, 03/04, page 324 of 462 pss: lvdcr: lvdsr: lvdres : lvdint : vreset: vint: extd: extu: vref: prescaler s low-voltage-detection control register low-voltage-detection status register low-voltage-detection reset signal low-voltage-detection interrupt signal reset detection voltage power-supply fall/rise detection voltage power supply drop detection voltage input pin power supply rise detection voltage input pin reference voltage input pin res lvdres interrupt control circuit lvdcr lvdsr internal reset signal power-on reset circuit low-voltage detection circuit interrupt request lvdint noise canceler noise canceler + ? ? figure 14.1 block diagram of power-on reset circuit and low-voltage detection circuit
rev. 4.00, 03/04, page 325 of 462 14.2 register descriptions the low-voltage detection circuit has the following registers. ? low-voltage-detection control register (lvdcr) ? low-voltage-detection status register (lvdsr) ? low-voltage detection counter (lvdcnt) 14.2.1 low-voltage detection control register (lvdcr) lvdcr is used to control whether or not the low-voltage detection circuit is used, settings for external input of power supply drop and rise detection voltages, the lvdr detection level setting, enabling or disabling of resets triggered by the low-voltage detection reset circuit (lvdr), and enabling or disabling of interrupts triggered by power supply voltage drops or rises. table 14.1 shows the relationship between lvdcr settings and function selections. refer to table 14.1 when making settings to lvdcr. bit bit name initial value r/w description 7lvde 0 * r/w lvd enable 0: low-voltage detection circuit not used (standby status) 1: low-voltage detection circuit used 6 ? 0 r/w this bit is reserved. 5 vintdsel 0 r/w power supply drop (lvdd) detection level external input select 0: lvdd detection level generated by on-chip ladder resistor 1: lvdd detection level input to extd pin 4 vintusel 0 r/w power supply rise (lvdu) detection level external input select 0: lvdu detection level generated by on-chip ladder resistor 1: lvdu detection level input to extu pin 3 lvdsel 0 * r/w lvdr detection level select 0: reset detection voltage 2.3 v (typ.) 1: reset detection voltage 3.3 v (typ.) select 2.3 v (typical) reset if voltage rise and drop detection interrupts are to be used. for reset detection only, select 3.3 v (typical) reset.
rev. 4.00, 03/04, page 326 of 462 bit bit name initial value r/w description 2 lvdre 0 * r/w lvdr enable 0: lvdr resets disabled 1: lvdr resets enabled 1 lvdde 0 r/w voltage drop interrupt enable 0: voltage drop interrupt requests disabled 1: voltage drop interrupt requests enabled 0 lvdue 0 r/w voltage rise interrupt enable 0: voltage rise interrupt requests disabled 1: voltage rise interrupt requests enabled note: * these bits are not initialized by resets trigged by lvdr. they are initialized by power-on resets and watchdog timer resets. table 14.1 lvdcr settings and select functions lvdcr settings select functions lvde lvdsel lvdre lvdde lvdue power-on reset lvdr low-voltage- detection falling interrupt low-voltage- detection rising interrupt 0 **** o ?? ? 11 10 0 o o ?? 10 01 0 o ? o ? 10 01 1 o ? oo 10 11 1 o oo o [legend] * means invalid. 14.2.2 low-voltage detection status register (lvdsr) lvdsr is used to control external input selection, indicates when the reference voltage is stable, and indicates if the power supply voltage goes below or above a specified range.
rev. 4.00, 03/04, page 327 of 462 bit bit name initial value r/w description 7ovf0 * r/w lvd reference voltage stabilized flag setting condition: when the low-voltage detection counter (lvdcnt) overflows clearing condition: when 0 is written after reading 1 6to4 ? 0 r/w these are read/write enabled reserved bits. 3 vrefsel 0 r/w reference voltage external input select 0: the on-chip circuit is used to generate the reference voltage 1: the reference voltage is input to the vref pin from an external source 2 ? 0 r/w this bit is reserved. it is always read as 0 and cannot be written to. 1 lvddf 0 * r/w lvd power supply voltage drop flag setting condition: when the power supply voltage drops below vint(d) clearing condition: when 0 is written after reading 1 0 lvduf 0 * r/w lvd power supply voltage rise flag setting condition: when the power supply voltage drops below vint(d) while the lvdue bit in lvdcr is set to 1, and it rises above vint(u) before dropping below vreset1 clearing condition: when 0 is written after reading 1 note: * these bits are initialized by resets trigged by lvdr. 14.2.3 low-voltage detection counter (lvdcnt) lvdcnt is a read-only 8-bit up-counter. counting begins when 1 is written to lvde. the counter increments using /4 as the clock source until it overflows by switching from h'ff to h'00, at which time the ovf bit in the lvdsr register is set to 1, indicating that the on-chip reference voltage generator has stabilized. if the lvd function is used, it is necessary to stand by until the counter has overflowed. the initial value of lvdcnt is h'00.
rev. 4.00, 03/04, page 328 of 462 14.3 operation 14.3.1 power-on reset circuit figure 14.2 shows the timing of the operation of the power-on reset circuit. as the power-supply voltage rises, the capacitor which is externally connected to the res pin is gradually charged via the on-chip pull-up resistor (typ. 100 k ? ). since the state of the res pin is transmitted within the chip, the prescaler s and the entire chip are in their reset states. when the level on the res pin reaches the specified value, the prescaler s is released from its reset state and it starts counting. the ovf signal is generated to release the internal reset signal after the prescaler s has counted 131,072 clock ( ) cycles. the noise cancellation circuit of approximately 100 ns is incorporated to prevent the incorrect operation of the chip by noise on the res pin. to achieve stable operation of this lsi, the power supply needs to rise to its full level and settles within the specified time. the maximum time required for the power supply to rise and settle after power has been supplied (t pwon ) is determined by the oscillation frequency (f osc ) and capacitance which is connected to res pin (c res ). if t pwon means the time required to reach 90 % of power supply voltage, the power supply circuit should be designed to satisfy the following formula. t pwon (ms) 80 c res ( f) 10/f osc (mhz) (t pwon 3000 ms, c res 0.22 f, and f osc = 10 in 2-mhz to 10-mhz operation) note that the power supply voltage (vcc) must fall below vpor = 100 mv and rise after charge on the res pinisremoved.toremovechargeonthe res pin, it is recommended that the diode should be placed near vcc. if the power supply voltage (vcc) rises from the point above vpor, a power-on reset may not occur. vcc pss-reset signal internal reset signal vss vss ovf 131,072 cycles pss counter starts reset released t pwon vpor figure 14.2 operational timing of power-on reset circuit
rev. 4.00, 03/04, page 329 of 462 14.3.2 low-voltage detection circuit lvdr (reset by low voltage detect) circuit: figure 14.3 shows the timing of the lvdr function. the lvdr enters the module-standby state after a power-on reset is canceled. to operate the lvdr, set the lvde bit in lvdcr to 1, wait for 100 s(t lvdon ) until the reference voltage and the low-voltage-detection power supply have stabilized, based on overflow of lvdcnt, then set the lvdre bit in lvdcr to 1. after that, the output settings of ports must be made. to cancel the low-voltage detection circuit, first the lvdre bit should be cleared to 0 and then the lvde bit should be cleared to 0. the lvde and lvdre bits must not be cleared to 0 simultaneously because incorrect operation may occur. when the power-supply voltage falls below the vreset voltage (typ. = 2.3 v or 3.3 v), the lvdr clears the lvdres signal to 0, and resets the prescaler s. the low-voltage detection reset state remains in place until a power-on reset is generated. when the power-supply voltage rises above the vreset voltage again, the prescaler s starts counting. it counts 131,072 clock ( )cycles,and then releases the internal reset signal. in this case, the lvde, lvdsel, and lvdre bits in lvdcr are not initialized. note that if the power supply voltage (vcc) falls below v lvdrmin = 1.0 v and then rises from that point, the low-voltage detection reset may not occur. if the power supply voltage (vcc) falls below vpor = 100 mv, a power-on reset occurs. v cc vreset v ss v lvdrmin ovf pss-reset signal internal reset signal 131,072 cycles pss counter starts reset released figure 14.3 operational timing of lvdr circuit
rev. 4.00, 03/04, page 330 of 462 lvdi (interrupt by low voltage detect) circuit: figure 14.4 shows the timing of lvdi functions. the lvdi enters the module-standby state after a power-on reset is canceled. to operate the lvdi, set the lvde bit in lvdcr to 1, wait for 100 s(t lvdon ) until the reference voltage and the low-voltage-detection power supply have stabilized, based on overflow of lvdnt, then set the lvdde and lvdue bits in lvdcr to 1. after that, the output settings of ports must be made. to cancel the low-voltage detection circuit, first the lvdde and lvdue bits should all be cleared to 0 and then the lvde bit should be cleared to 0. the lvde bit must not be cleared to 0 at the same timing as the lvdde and lvdue bits because incorrect operation may occur. when the power-supply voltage falls below vint (d) (typ. = 3.7 v) voltage, the lvdi clears the lvdint signal to 0 and the lvddf bit in lvdsr is set to 1. if the lvdde bit is 1 at this time, an irq0 interrupt request is simultaneously generated. in this case, the necessary data must be saved in the external eeprom, etc, and a transition must be made to standby mode, watch mode, or subsleep mode. until this processing is completed, the power supply voltage must be higher than the lower limit of the guaranteed operating voltage. when the power-supply voltage does not fall below vreset1 (typ. = 2.3 v) voltage but rises above vint (u) (typ. = 4.0 v) voltage, the lvdi sets the lvdint signal to 1. if the lvdue bit is 1 at this time, the lvduf bit in lvdsr is set to 1 and an irq0 interrupt request is simultaneously generated. if the power supply voltage (vcc) falls below vreset1 (typ. = 2.3 v) voltage, the lvdr function is performed. vcc vint (d) vint (u) vss lvddf lvdue lvduf irq0 interrupt generated irq0 interrupt generated lvdde vreset1 figure 14.4 operational timing of lvdi circuit
rev. 4.00, 03/04, page 331 of 462 the reference voltage, power supply voltage drop detection level, and power supply voltage rise detection level can be input to the lsi from external sources via the vref, extd, and extu pins. figure 14.5 shows the operational timing using input from the vref, extd, and extu pins. first, make sure that the voltages input to pins extd and extu are set to higher levels than the interrupt detection voltage vexd. after initial settings are made, a power supply drop interrupt is generated if the extd input voltage drops below vexd. after a power supply drop interrupt is generated, if the external power supply voltage rises and the extu input voltage rises higher than vexd, a power supply rise interrupt is generated. as with the on-chip circuit, the above function should be used in conjunction with lvdr (vreset1) when the lvdi function is used. lvdintd extd input voltage extu input voltage vreset1 vexd (4) (3) (2) (1) v ss lvdintu lvddf irq0 interrupt generated irq0 interrupt generated lvduf external power supply voltage figure 14.5 operational timing of low-voltage detection interrupt circuit (using pins vref, extd, and extu)
rev. 4.00, 03/04, page 332 of 462 figure 14.6 shows a usage example for the lvd function employing pins vref, extd, and extu. setting conditions: vref = 1.3 v external input (this vref value results in a vreset value of 2.5 v.) power supply drop detection voltage input of 2.7 v from extd power supply rise detection voltage input of 2.9 v from extu 1 m ? ? ? ? lvdres interrupt controller lvdcr lvdsr interrupt request lvdint + ? + ? figure 14.6 lvd function usage example employing pins vref, extd, and extu below is an explanation of the method for calculating the external resistor values when using the vref, extd, and extu pins for input of reference and detection voltages from sources external to the lsi. procedure: 1. first, determine the overall resistance value, r. the current consumed by the resistor is determined by the value of r. a lower r will result in a greater current flow, and a higher r will result in a reduced current flow. the value of r is dependent on the configuration of the system in which the lsi is installed. 2. determine the power supply drop detection voltage (vint(d) and the power supply rise detection voltage (vint(u). 3. using a resistance value calculation table like the one shown below, plug in values for r, vreset1, vint(d), and vint(u) to calculate the values of vref, r1, r2, and r3.
rev. 4.00, 03/04, page 333 of 462 resistance value calculation table ex. no vref (v) r (k ? ? ? ? ) vreset1 vint(d) vint(u) r1 (k ? ? ? ? )r2(k ? ? ? ? )r3(k ? ? ? ? ) 1 1.30 1000 2.5 2.7 2.9 517 33 450 2 1.41 1000 2.7 2.9 3 514 16 470 3 1.57 1000 3 3.2 3.5 511 42 447 4 2.09 1000 4 4.5 4.7 536 20 444 4. using an error calculation table like the one shown below, plug in values for r1, r2, r3, and vref to calculate the deviation of vreset1, vint(d), and vint(u). make sure to double check the maximum and minimum values for each value. error calculation table resistance value error (%) vref (v) r1 (k ? ? ? ? ) r2 (k ? ? ? ? ) r3 (k ? ? ? ? ) 5 comparator error (v) vreset1 (v) vint(d) (v) vint(u) (v) 1.3 517 33 450 r1+err, r2/r3-err 0.1 2.59 2.94 3.15 0 2.49 2.84 3.05 -0.1 2.39 2.74 2.95 r1-err, r2/r3+err 0.1 2.59 2.66 2.85 0 2.49 2.56 2.75 -0.1 2.39 2.46 2.65 r1/r2/r3 no err 0.1 2.59 2.79 2.99 0 2.49 2.69 2.89 -0.1 2.39 2.59 2.79 r1/r2+err, r3-err 0.1 2.59 2.93 3.16 0 2.49 2.83 3.06 -0.1 2.39 2.73 2.96 r1/r2-err, r3+err 0.1 2.59 2.67 2.84 0 2.49 2.57 2.74 -0.1 2.39 2.47 2.64
rev. 4.00, 03/04, page 334 of 462 procedures for clearing settings when using lvdr and lvdi: to operate or release the low-voltage detection circuit normally, follow the procedure described below. figure 14.7 shows the timing for the operation and release of the low-voltage detection circuit. 1. to operate the low-voltage detection circuit, set the lvde bit in lvdcr to 1. 2. wait for 100 s(t lvdon ) until the reference voltage and the low-voltage-detection power supply have stabilized, based on overflow of lvdnt. then, clear the lvddf and lvduf bits in lvdsr to 0 and set the lvdre, lvdde, and lvdue bits in lvdcr to 1, as required. 3. to release the low-voltage detection circuit, start by clearing all of the lvdre, lvdde, and lvdue bits to 0. then clear the lvde bit to 0. the lvde bit must not be cleared to 0 at the same timing as the lvdre, lvdde, and lvdue bits because incorrect operation may occur. lvdre lvdde lvdue t lvdon lvde figure 14.7 timing for operation/release of low-voltage detection circuit
psckt00a_000020020200 rev. 4.00, 03/04, page 335 of 462 section 15 power supply circuit (h8/38104 group only) this lsi incorporates an internal power supply step-down circuit. use of this circuit enables the internal power supply to be fixed at a constant level of approximately 3.0 v, independently of the voltage of the power supply connected to the external v cc pin. as a result, the current consumed when an external power supply is used at 3.0 v or above can be held down to virtually the same low level as when used at approximately 3.0 v. if the external power supply is 3.0 v or below, the internal voltage will be practically the same as the external voltage. it is, of course, also possible to use the same level of external power supply voltage and internal power supply voltage without using the internal power supply step-down circuit. 15.1 when using internal power supply step-down circuit connect the external power supply to the v cc pin, and connect a capacitance of approximately 0.1 f between cv cc and v ss , as shown in figure 15.1. the internal step-down circuit is made effective simply by adding this external circuit. in the external circuit interface, the external power supply voltage connected to v cc and the gnd potential connected to v ss are the reference levels. for example, for port input/output levels, the v cc level is the reference for the high level, and the v ss level is that for the low level. the a/d converter analog power supply is not affected by the internal step-down circuit. cv cc v ss internal logic step-down circuit internal power supply stabilization capacitance (approx. 0.1 f) v cc v cc = 2.7 to 5.5 v figure 15.1 power supply connection when internal step-down circuit is used
rev. 4.00, 03/04, page 336 of 462 15.2 when not using internal power supply step-down circuit when the internal power supply step-down circuit is not used, connect the external power supply to the cv cc pin and v cc pin, as shown in figure 15.2. the external power supply is then input directly to the internal power supply. the permissible range for the power supply voltage is 2.7 v to 3.6 v. operation cannot be guaranteed if a voltage outside this range (less than 3.0 v or more than 3.6 v) is input. cv cc v ss internal logic step-down circuit internal power supply v cc v cc = 2.7 to 3.6 v figure 15.2 power supply connection when internal step-down circuit is not used
rev. 4.00, 03/04, page 337 of 462 section 16 list of registers the register list gives information on the on-chip i/o register addresses, how the register bits are configured, and the register states in each operating mode. the information is given as shown below. 1. register addresses (address order) ? registers are listed from the lower allocation addresses. ? registers are classified by functional modules. ? the data bus width is indicated. ? the number of access states is indicated. 2. register bits ? bit configurations of the registers are described in the same order as the register addresses. ? reserved bits are indicated by ? in the bit name column. ? when registers consist of 16 bits, bits are described from the msb side. 3. register states in each operating mode ? register states are described in the same order as the register addresses. ? the register states described here are for the basic operating modes. if there is a specific reset for an on-chip peripheral module, refer to the section on that on-chip peripheral module.
rev. 4.00, 03/04, page 338 of 462 16.1 register addresses (address order) the data bus width indicates the numbers of bits by which the register is accessed. the number of access states indicates the number of states based on the specified reference clock. register name abbre- viation bit no address module name data bus width access state flash memory control register 1 flmcr1 8 h'f020 rom 8 2 flash memory control register 2 flmcr2 8 h'f021 rom 8 2 flash memory power control register flpwcr 8 h'f022 rom 8 2 erase block register ebr 8 h'f023 rom 8 2 flash memory enable register fenr 8 h'f02b rom 8 2 low-voltage detection control register * 4 lvdcr 8 h'ff86 lvd 8 2 low-voltage detection status register * 4 lvdsr 8 h'ff87 lvd 8 2 event counter pwm compare register h ecpwcrh 8 h'ff8c aec * 1 82 event counter pwm compare register l ecpwcrl 8 h'ff8d aec * 1 82 event counter pwm data register h ecpwdrh 8 h'ff8e aec * 1 82 event counter pwm data register l ecpwdrl 8 h'ff8f aec * 1 82 wakeup edge select register wegr 8 h'ff90 interrupts 8 2 serial port control register spcr 8 h'ff91 sci3 8 2 input pin edge select register aegsr 8 h'ff92 aec * 1 82 event counter control register eccr 8 h'ff94 aec * 1 82 event counter control/status register eccsr 8 h'ff95 aec * 1 82 event counter h ech 8 h'ff96 aec * 1 82 event counter l ecl 8 h'ff97 aec * 1 82 serial mode register smr 8 h'ffa8 sci3 8 3 bit rate register brr 8 h'ffa9 sci3 8 3 serial control register 3 scr3 8 h'ffaa sci3 8 3 transmit data register tdr 8 h'ffab sci3 8 3 serial status register ssr 8 h'ffac sci3 8 3
rev. 4.00, 03/04, page 339 of 462 register name abbre- viation bit no address module name data bus width access state receive data register rdr 8 h'ffad sci3 8 3 timer mode register a tma 8 h'ffb0 timer a 8 2 timer counter a tca 8 h'ffb1 timer a 8 2 timer control/status register w tcsrw 8 h'ffb2 wdt * 2 82 timer counter w tcw 8 h'ffb3 wdt * 2 82 timer control register f tcrf 8 h'ffb6 timer f 8 2 timer control status register f tcsrf 8 h'ffb7 timer f 8 2 8-bit timer counter fh tcfh 8 h'ffb8 timer f 8 2 8-bit timer counter fl tcfl 8 h'ffb9 timer f 8 2 output compare register fh ocrfh 8 h'ffba timer f 8 2 output compare register fl ocrfl 8 h'ffbb timer f 8 2 lcd port control register lpcr 8 h'ffc0 lcd * 3 82 lcd control register lcr 8 h'ffc1 lcd * 3 82 lcd control register 2 lcr2 8 h'ffc2 lcd * 3 82 low-voltage detection counter * 4 lvdcnt 8 h'ffc3 lvd 8 2 a/d result register h adrrh 8 h'ffc4 a/d converter 8 2 a/d result register l adrrl 8 h'ffc5 a/d converter 8 2 a/d mode register amr 8 h'ffc6 a/d converter 8 2 a/d start register adsr 8 h'ffc7 a/d converter 8 2 port mode register 2 pmr2 8 h'ffc9 i/o port 8 2 port mode register 3 pmr3 8 h'ffca i/o port 8 2 port mode register 5 pmr5 8 h'ffcc i/o port 8 2 pwm2 control register pwcr2 8 h'ffcd 10-bit pwm 8 2 pwm2 data register u pwdru2 8 h'ffce 10-bit pwm 8 2 pwm2 data register l pwdrl2 8 h'ffcf 10-bit pwm 8 2 pwm1 control register pwcr1 8 h'ffd0 10-bit pwm 8 2 pwm1 data register u pwdru1 8 h'ffd1 10-bit pwm 8 2 pwm1 data register l pwdrl1 8 h'ffd2 10-bit pwm 8 2 port data register 3 pdr3 8 h'ffd6 i/o port 8 2 port data register 4 pdr4 8 h'ffd7 i/o port 8 2 port data register 5 pdr5 8 h'ffd8 i/o port 8 2 port data register 6 pdr6 8 h'ffd9 i/o port 8 2 port data register 7 pdr7 8 h'ffda i/o port 8 2
rev. 4.00, 03/04, page 340 of 462 register name abbre- viation bit no address module name data bus width access state port data register 8 pdr8 8 h'ffdb i/o port 8 2 port data register 9 pdr9 8 h'ffdc i/o port 8 2 port data register a pdra 8 h'ffdd i/o port 8 2 port data register b pdrb 8 h'ffde i/o port 8 2 port pull-up control register 3 pucr3 8 h'ffe1 i/o port 8 2 port pull-up control register 5 pucr5 8 h'ffe2 i/o port 8 2 port pull-up control register 6 pucr6 8 h'ffe3 i/o port 8 2 port control register 3 pcr3 8 h'ffe6 i/o port 8 2 port control register 4 pcr4 8 h'ffe7 i/o port 8 2 port control register 5 pcr5 8 h'ffe8 i/o port 8 2 port control register 6 pcr6 8 h'ffe9 i/o port 8 2 port control register 7 pcr7 8 h'ffea i/o port 8 2 port control register 8 pcr8 8 h'ffeb i/o port 8 2 port mode register 9 pmr9 8 h'ffec i/o port 8 2 port control register a pcra 8 h'ffed i/o port 8 2 port mode register b pmrb 8 h'ffee i/o port 8 2 system control register 1 syscr1 8 h'fff0 system 8 2 system control register 2 syscr2 8 h'fff1 system 8 2 irq edge select register iegr 8 h'fff2 interrupts 8 2 interrupt enable register 1 ienr1 8 h'fff3 interrupts 8 2 interrupt enable register 2 ienr2 8 h'fff4 interrupts 8 2 oscillator control register * 4 osccr 8 h'fff5 cpg 8 2 interrupt request register 1 irr1 8 h'fff6 interrupts 8 2 interrupt request register 2 irr2 8 h'fff7 interrupts 8 2 timer mode register w * 4 tmw 8 h'fff8 wdt * 2 82 wakeup interrupt request register iwpr 8 h?fff9 interrupts 8 2 clock stop register 1 ckstpr1 8 h'fffa system 8 2 clock stop register 2 ckstpr2 8 h'fffb system 8 2 notes: 1. aec: asynchronous event counter 2. wdt: watchdog timer 3. lcd: lcd controller/driver 4. h8/38104 group only
rev. 4.00, 03/04, page 341 of 462 16.2 register bits register bit names of the on-chip peripheral modules are described below. register abbreviation bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name flmcr1 ? swe esu psu ev pv e p rom flmcr2fler??????? flpwcrpdwnd??????? ebr ? ? ? eb4 eb3 eb2 eb1 eb0 fenrflshe??????? lvdcr * 4 lvde ? vintdsel vintusel lvdsl lvdre lvdde lvdue lvdsr * 4 ovf ? ? ? vrefsel ? lvddf lvduf low- voltage detect circuit ecpwcrh ecpwcrh7 ecpwcrh6 ecpwcrh5 ecpwcrh4 ecpwcrh3 ecpwcrh2 ecpwcrh1 ecpwcrh0 aec * 1 ecpwcrl ecpwcrl7 ecpwcrl6 ecpwcrl5 ecpwcrl4 ecpwcrl3 ecpwcrl2 ecpwcrl1 ecpwcrl0 ecpwdrh ecpwdrh7 ecpwdrh6 ecpwdrh5 ecpwdrh4 ecpwdrh3 ecpwdrh2 ecpwdrh1 ecpwdrh0 ecpwdrl ecpwdrl7 ecpwdrl6 ecpwdrl5 ecpwdrl4 ecpwdrl3 ecpwdrl2 ecpwdrl1 ecpwdrl0 wegr wkegs7 wkegs6 wkegs5 wkegs4 wkegs3 wkegs2 wkegs1 wkegs0 interrupts spcr ? ? spc32 ? scinv3 scinv2 ? ? sci3 aegsr ahegs1 ahegs0 alegs1 alegs0 aiegs1 aiegs0 ecpwme ? aec * 1 eccr ackh1 ackh0 ackl1 ackl0 pwck2 pwck1 pwck0 ? eccsr ovh ovl ? ch2 cueh cuel crch crcl ech ech7 ech6 ech5 ech4 ech3 ech2 ech1 ech0 ecl ecl7 ecl6 ecl5 ecl4 ecl3 ecl2 ecl1 ecl0 smr com chr pe pm stop mp cks1 cks0 sci3 brr brr7 brr6 brr5 brr4 brr3 brr2 brr1 brr0 scr3 tie rie te re mpie teie cke1 cke0 tdr tdr7 tdr6 tdr5 tdr4 tdr3 tdr2 tdr1 tdr0 ssr tdre rdrf oer fer per tend mpbr mpbt rdr rdr7 rdr6 rdr5 rdr4 rdr3 rdr2 rdr1 rdr0 tma ? ? ? ? tma3 tma2 tma1 tma0 timer a tca tca7 tca6 tca5 tca4 tca3 tca2 tca1 tca0 tcsrw b6wi tcwe b4wi tcsrwe b2wi wdon bowi wrst wdt * 2 tcw tcw7 tcw6 tcw5 tcw4 tcw3 tcw2 tcw1 tcw0
rev. 4.00, 03/04, page 342 of 462 register abbreviation bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name tcrf tolh cksh2 cksh1 cksh0 toll cksl2 cksl1 cksl0 timer f tcsrf ovfh cmfh ovieh cclrh ovfl cmfl oviel cclrl tcfh tcfh7 tcfh6 tcfh5 tcfh4 tcfh3 tcfh2 tcfh1 tcfh0 tcfl tcfl7 tcfl6 tcfl5 tcfl4 tcfl3 tcfl2 tcfl1 tcfl0 ocrfh ocrfh7 ocrfh6 ocrfh5 ocrfh4 ocrfh3 ocrfh2 ocrfh1 ocrfh0 ocrfl ocrfl7 ocrfl6 ocrfl5 ocrfl4 ocrfl3 ocrfl2 ocrfl1 ocrfl0 lpcr dts1 dts0 cmx ? sgs3 sgs2 sgs1 sgs0 lcd * 3 lcr ? psw act disp cks3 cks2 cks1 cks0 lcr2 lcdab ? ? ? cds3 * 4 cds2 * 4 cds1 * 4 cds0 * 4 lvdcnt * 4 cnt7 cnt6 cnt5 cnt4 cnt3 cnt2 cnt1 cnt0 low- voltage detect circuit adrrh adr9 adr8 adr7 adr6 adr5 adr4 adr3 adr2 adrrl adr1 adr0 ? ? ? ? ? ? a/d converter amr cks ? ? ? ch3 ch2 ch1 ch0 adsr adsf ? ? ? ? ? ? ? pmr2??pof1??wdcks?irq0i/oport pmr3 aevl aevh ? ? ? tmofh tmofl ? pmr5 wkp7 wkp6 wkp5 wkp4 wkp3 wkp2 wkp1 wkp0 pwcr2????? pwcr22 * 4 pwcr21 pwcr20 pwdru2 ? ? ? ? ? ? pwdru21 pwdru20 10-bit pwm pwdrl2 pwdrl27 pwdrl26 pwdrl25 pwdrl24 pwdrl23 pwdrl22 pwdrl21 pwdrl20 pwcr1????? pwcr12 * 4 pwcr11 pwcr10 pwdru1 ? ? ? ? ? ? pwdru11 pwdru10 pwdrl1 pwdrl17 pwdrl16 pwdrl15 pwdrl14 pwdrl13 pwdrl12 pwdrl11 pwdrl10 pdr3 p37 p36 p35 p34 p33 p32 p31 ? i/o port pdr4????p43p42p41p40 pdr5 p57 p56 p55 p54 p53 p52 p51 p50 pdr6 p67 p66 p65 p64 p63 p62 p61 p60 pdr7 p77 p76 p75 p74 p73 p72 p71 p70 pdr8???????p80 pdr9 ? ? p95 p94 p93 p92 p91 p90 pdra ? ? ? ? pa3 pa2 pa1 pa0 pdrb ? ? ? ? pb3 pb2 pb1 pb0 pucr3 pucr37 pucr36 pucr35 pucr34 pucr33 pucr32 pucr31 ?
rev. 4.00, 03/04, page 343 of 462 register abbreviation bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name pucr5 pucr57 pucr56 pucr55 pucr54 pucr53 pucr52 pucr51 pucr50 i/o port pucr6 pucr67 pucr66 pucr65 pucr64 pucr63 pucr62 pucr61 pucr60 pcr3 pcr37 pcr36 pcr35 pcr34 pcr33 pcr32 pcr31 ? pcr4 ? ? ? ? ? pcr42 pcr41 pcr40 pcr5 pcr57 pcr56 pcr55 pcr54 pcr53 pcr52 pcr51 pcr50 pcr6 pcr67 pcr66 pcr65 pcr64 pcr63 pcr62 pcr61 pcr60 pcr7 pcr77 pcr76 pcr75 pcr74 pcr73 pcr72 pcr71 pcr70 pcr8???????pcr80 pmr9????pioff?pwm2pwm1 pcra ? ? ? ? pcra3 pcra2 pcra1 pcra0 i/o port pmrb????irq1??? syscr1 ssby sts2 sts1 sts0 lson ? ma1 ma0 system syscr2 ? ? ? nesel dton mson sa1 sa0 iegr??????ieg1ieg0interrupts ienr1 ienta ? ienwp ? ? ienec2 ien1 ien0 ienr2 iendt ienad ? ? ientfh ientfl ? ienec osccr * 4 substp ? ? ? ? irqaecf oscf ? cpg irr1 irrta ? ? ? ? irrec2 irri1 irri0 irr2 irrdt irrad ? ? irrtfh irrtfl ? irrec tmw * 4 ? ? ? ? cks3 cks2 cks1 cks0 wdt * 2 iwpr iwpf7 iwpf6 iwpf5 iwpf4 iwpf3 iwpf2 iwpf1 iwpf0 ckstpr1 ? ? s32ckstp adckstp ? tfckstp ? tackstp system ckstpr2 lvdckstp * 4 ?? pw2ckstp aeckstp wdckstp pw1ckstp ldckstp notes: 1 . aec: asynchronous event counter 2. wdt: watchdog timer 3. lcd: lcd controller/driver 4. h8/38104 group only
rev. 4.00, 03/04, page 344 of 462 16.3 register states in each operating mode register abbreviation reset active sleep watch subactive subsleep standby module flmcr1 initialized ? ? initialized initialized initialized initialized rom flmcr2initialized?????? flpwcrinitialized?????? ebr initialized ? ? initialized initialized initialized initialized fenr initialized?????? lvdcr * 4 initialized?????? lvdsr * 4 initialized?????? low- voltage detect circuit ecpwcrhinitialized??????aec * 1 ecpwcrlinitialized?????? ecpwdrhinitialized?????? ecpwdrlinitialized?????? wegr initialized ? ? ? ? ? ? interrupts spcr initialized ? ? ? ? ? ? sci3 aegsr initialized ? ? ? ? ? ? aec * 1 eccrinitialized?????? eccsr initialized ? ? ? ? ? ? ech initialized ? ? ? ? ? ? ecl initialized ? ? ? ? ? ? smr initialized ? ? initialized ? ? initialized sci3 brr initialized ? ? initialized ? ? initialized scr3 initialized ? ? initialized ? ? initialized tdr initialized ? ? initialized ? ? initialized ssr initialized ? ? initialized ? ? initialized rdr initialized ? ? initialized ? ? initialized tma initialized ? ? ? ? ? ? timer a tca initialized ? ? ? ? ? ? tcsrw initialized ? ? ? ? ? ? wdt * 2 tcw initialized ? ? ? ? ? ?
rev. 4.00, 03/04, page 345 of 462 register abbreviation reset active sleep watch subactive subsleep standby module tcrf initialized??????timerf tcsrf initialized ? ? ? ? ? ? tcfh initialized?????? tcfl initialized?????? ocrfh initialized ? ? ? ? ? ? ocrfl initialized ? ? ? ? ? ? lpcr initialized??????lcd * 3 lcr initialized ? ? ? ? ? ? lcr2 initialized?????? lvdcnt * 4 initialized??????low- voltage detect circuit adrrh ? ? ? ? ? ? ? adrrl ? ? ? ? ? ? ? a/d converter amr initialized ? ? ? ? ? ? adsr initialized ? ? initialized initialized initialized initialized pmr2 initialized??????i/oport pmr3 initialized?????? pmr5 initialized?????? pwcr2initialized?????? pwdru2 initialized ? ? ? ? ? ? 10-bit pwm pwdrl2 initialized ? ? ? ? ? ? pwcr1initialized?????? pwdru1 initialized ? ? ? ? ? ? pwdrl1 initialized ? ? ? ? ? ? pdr3 initialized??????i/oport pdr4 initialized?????? pdr5 initialized ?????? pdr6 initialized ?????? pdr7 initialized ?????? pdr8 initialized ?????? pdr9 initialized ?????? pdra initialized ?????? pdrb initialized ?????? pucr3 initialized ??????
rev. 4.00, 03/04, page 346 of 462 register abbreviation reset active sleep watch subactive subsleep standby module pucr5 initialized ?????? i/o port pucr6 initialized ?????? pcr3 initialized ?????? pcr4 initialized ?????? pcr5 initialized ?????? pcr6 initialized ?????? pcr7 initialized ?????? pcr8 initialized ?????? pmr9 initialized ?????? pcra initialized ?????? pmrb initialized ?????? syscr1 initialized ?????? system syscr2 initialized ?????? iegr initialized ?????? interrupts ienr1 initialized ?????? ienr2 initialized ?????? osccr * 4 initialized ?????? cpg irr1 initialized ?????? irr2 initialized ?????? tmw * 4 initialized ?????? wdt * 2 iwpr initialized ? ????? ckstpr1 initialized ?????? system ckstpr2 initialized ?? ???? notes: ? is not initialized 1 . aec: asynchronous event counter 2. wdt: watchdog timer 3. lcd: lcd controller/driver 4. h8/38104 group only
rev. 4.00, 03/04, page 347 of 462 section 17 electrical characteristics 17.1 absolute maximum ratings of h8/3802 group table 17.1 lists the absolute maximum ratings. table 17.1 absolute maximum ratings item symbol value unit note power supply voltage v cc ?0.3 to +7.0 v * analog power supply voltage av cc ?0.3 to +7.0 v programming voltage v pp ?0.3to+13.0 v input voltage other than port b and irqaec v in ?0.3tov cc +0.3 v port b av in ?0.3toav cc +0.3 v irqaec hv in ?0.3 to +7.3 v port 9 pin voltage v p9 ?0.3 to +7.3 v regular specifications: ?20 to +75 operating temperature t opr wide-range temperature specifications: ?40 to +85 c storage temperature t stg ?55 to +125 c note: * permanent damage may result if maximum ratings are exceeded. normal operation should be under the conditions specified in electrical characteristics. exceeding these values can result in incorrect operation and reduced reliability.
rev. 4.00, 03/04, page 348 of 462 17.2 electrical characteristics of h8/3802 group 17.2.1 power supply voltage and operating ranges power supply voltage and oscillation frequency range 38.4 1.8 3.0 5.5 v cc (v) f w (khz) 32.768 4.5 16.0 2.0 10.0 4.0 1.8 2.7 4.5 5.5 v cc (v) fosc (mhz) active (high-speed) mode sleep (high-speed) mode note 1: the fosc values are those when a resonator is used; when an external clock is used, the minimum value of fosc is 1 mhz. all operating modes note 2: when a resonator is used, hold vcc at 2.2 v to 5.5 v from power-on until the oscillation stabilization time has elapsed.
rev. 4.00, 03/04, page 349 of 462 power supply voltage and operating frequency range subactive mode subsleep mode (except cpu) watch mode (except cpu) 16.384 8.192 4.096 1.8 3.6 5.5 v cc (v) sub (khz) 19.2 9.6 4.8 8.0 (0.5) 5.0 2.0 1.0 1.8 2.7 4.5 5.5 v cc (v) (mhz) 1000 (7.8125) 625 250 15.625 1.8 2.7 4.5 5.5 v cc (v) ( khz) active (medium-speed) mode sleep (medium-speed) mode (except a/d converter) note 2: the values in parentheses is the minimum operating frequency when an external clock is input. when using a resonator, the minimum operating frequency ( ) is 15.625 khz. active (high-speed) mode sleep (high-speed) mode (except cpu) note 1: the values in parentheses is the minimum operating frequency when an external clock is input. when using a resonator, the minimum operating frequency ( ) is 1 mhz.
rev. 4.00, 03/04, page 350 of 462 analog power supply voltage and a/d converter operating range (mhz) (0.5) 5.0 1.0 1.8 2.7 4.5 5.5 av cc (v) active (high-speed) mode sleep (high-speed) mode note: when avcc = 1.8 v to 2.7 v, the operating range is limited to = 1.0 mhz when using a resonator and is = 0.5 mhz to 1.0 mhz when using an external clock. (khz) 500 1000 625 1.8 2.7 4.5 5.5 av cc (v) active (medium-speed) mode sleep (medium-speed) mode
rev. 4.00, 03/04, page 351 of 462 17.2.2 dc characteristics table 17.2 lists the dc characteristics. table 17.2 dc characteristics (1) v cc = 1.8 v to 5.5 v, av cc = 1.8 v to 5.5 v, v ss =av ss = 0.0 v, unless otherwise specified (including subactive mode), t a = ?20c to +75c (product with regular specifications), t a =? 40c to +85c (product with wide-range temperature specifications), t a =+75c(baredie product) values item symbol applicable pins test condition min typ max unit notes input high voltage v ih res , wkp0 to wkp7 , irq0 , irq1, aevl, aevh, v cc = 4.0 v to 5.5 v v cc 0.8 ? v cc +0.3 v sck32 other than above v cc 0.9 ? v cc +0.3 rxd32 v cc = 4.0 v to 5.5 v v cc 0.7 ? v cc +0.3 v other than above v cc 0.8 ? v cc +0.3 osc 1 v cc = 4.0 v to 5.5 v v cc 0.8 ? v cc +0.3 v other than above v cc 0.9 ? v cc +0.3 x1 v cc = 1.8 v to 5.5 v v cc 0.9 ? v cc +0.3 v p31 to p37, p40 to p43, p50 to p57, v cc = 4.0 v to 5.5 v v cc 0.7 ? v cc +0.3 v p60 to p67, p70 to p77, p80, pa0 to pa3 other than above v cc 0.8 ? v cc +0.3 pb0 to pb3 v cc = 4.0 v to 5.5 v v cc 0.7 ? av cc +0.3 v other than above v cc 0.8 ? av cc +0.3 irqaec v cc = 4.0 v to 5.5 v v cc 0.8 ? 7.3 v other than above v cc 0.9 ? 7.3 note: connect the test pin to v ss .
rev. 4.00, 03/04, page 352 of 462 table 17.2 dc characteristics (2) v cc = 1.8 v to 5.5 v, av cc = 1.8 v to 5.5 v, v ss =av ss = 0.0 v, unless otherwise specified (including subactive mode), t a = ?20c to +75c (product with regular specifications), t a =? 40c to +85c (product with wide-range temperature specifications), t a = +75c (bare die product) values item symbol applicable pins test condition min typ max unit notes input low voltage v il res , wkp0 to wkp7 , irq0 , irq1, irqaec, v cc = 4.0 v to 5.5 v ? 0.3 ? v cc 0.2 v aevl, aevh, sck32 other than above ? 0.3 ? v cc 0.1 rxd32 v cc = 4.0 v to 5.5 v ? 0.3 ? v cc 0.3 v other than above ? 0.3 ? v cc 0.2 osc1 v cc = 4.0 v to 5.5 v ? 0.3 ? v cc 0.2 v other than above ? 0.3 ? v cc 0.1 x1 v cc = 1.8 v to 5.5 v ? 0.3 ? v cc 0.1 v p31 to p37, p40 to p43, p50 to p57, v cc = 4.0 v to 5.5 v ? 0.3 ? v cc 0.3 v p60 to p67, p70 to p77, p80, pa0 to pa3, pb0 to pb3 other than above ? 0.3 ? v cc 0.2 v oh v cc = 4.0 v to 5.5 v ?i oh =1.0ma v cc ?1.0 ? ? v output high voltage v cc = 4.0 v to 5.5 v ?i oh =0.5ma v cc ?0.5 ? ? p31 to p37, p40 to p42, p50 to p57, p60 to p67, p70 to p77, p80, pa0 to pa3 ?i oh =0.1ma v cc ?0.3 ? ?
rev. 4.00, 03/04, page 353 of 462 table 17.2 dc characteristics (3) v cc = 1.8 v to 5.5 v, av cc = 1.8 v to 5.5 v, v ss =av ss = 0.0 v, unless otherwise specified (including subactive mode), t a = ?20c to +75c (product with regular specifications), t a =? 40c to +85c (product with wide-range temperature specifications), t a = +75c (bare die product) values item symbol applicable pins test condition min typ max unit notes output low voltage v ol p40 to p42 v cc = 4.0 v to 5.5 v i ol =1.6ma ??0.6v i ol =0.4ma ? ? 0.5 p50 to p57, p60 to p67, p70 to p77, p80, pa0 to pa3 i ol =0.4ma ? ? 0.5 p31 to p37 v cc = 4.0 v to 5.5 v i ol =10ma ??1.5 v cc = 4.0 v to 5.5 v i ol =1.6ma ??0.6 i ol =0.4ma ? ? 0.5 p90 to p92 v cc = 2.2 v to 5.5 v i ol =25ma ??0.5 * 5 i ol =15ma i ol =10ma * 6 p93 to p95 i ol =10ma ? ? 0.5 |i il | res ,p43 v in =0.5vtov cc ? 0.5 v ? ? 20.0 a * 2 ??1.0 * 1 osc1, x1, p31 to p37, p40 to p42, p50 to p57, p60 to p67, p70 to p77, p80, irqaec, pa0 to pa3, p90 to p95 v in =0.5vtov cc ? 0.5 v ??1.0a input/ output leakage current pb0 to pb3 v in =0.5vtoav cc ?0.5v ??1.0
rev. 4.00, 03/04, page 354 of 462 table 17.2 dc characteristics (4) v cc = 1.8 v to 5.5 v, av cc = 1.8 v to 5.5 v, v ss =av ss = 0.0 v, unless otherwise specified (including subactive mode), t a = ?20c to +75c (product with regular specifications), t a =? 40c to +85c (product with wide-range temperature specifications), t a = +75c (bare die product) values item symbol applicable pins test condition min typ max unit notes ?i p v cc =5.0v, v in =0.0v 50.0 ? 300.0 a pull-up mos current p31 to p37, p50 to p57, p60 to p67 v cc =2.7v, v in =0.0v ? 35.0 ? reference value input capaci- tance c in all input pins except power supply, res , p43, irqaec, pb0 to pb3 pins f=1mhz, v in =0.0v, t a =25c ? ? 15.0 pf irqaec ? ? 30.0 res ? ? 80.0 * 2 ? ? 15.0 * 1 p43 ? ? 50.0 * 2 ? ? 15.0 * 1 pb0 to pb3 ? ? 15.0 i ope1 v cc active (high-speed) mode v cc =5.0v, f osc =10mhz ? 7.0 10.0 ma * 3 * 4 active mode current consump- tion i ope2 v cc active (medium- speed) mode v cc =5.0v, f osc =10mhz, osc /128 ?2.23.0ma * 3 * 4 sleep mode current consump- tion i sleep v cc v cc =5.0v, f osc =10mhz ?3.85.0ma * 3 * 4
rev. 4.00, 03/04, page 355 of 462 table 17.2 dc characteristics (5) v cc = 1.8 v to 5.5 v, av cc = 1.8 v to 5.5 v, v ss =av ss = 0.0 v, unless otherwise specified (including subactive mode), t a = ?20c to +75c (product with regular specifications), t a =? 40c to +85c (product with wide-range temperature specifications), t a = +75c (bare die product) values item symbol applicable pins test condition min typ max unit notes subactive mode current consump- tion i sub v cc v cc =2.7v, lcd on, 32-khz crystal resonator used ( sub = w /2) ? 15.0 30.0 a * 3 * 4 v cc =2.7v, lcd on, 32-khz crystal resonator used ( sub = w /8) ?8.0? * 3 * 4 reference value subsleep mode current consump- tion i subsp v cc v cc =2.7v, lcd on, 32-khz crystal resonator used ( sub = w /2) ? 7.5 16.0 a * 3 * 4 3.8 a * 2 * 3 * 4 watch mode current consump- tion i watch v cc v cc =2.7v, lcd not used, 32-khz crystal resonator used ? 2.8 6.0 * 1 * 3 * 4 standby mode current consump- tion i stby v cc 32-khz crystal resonator not used ?1.05.0 a * 3 * 4 ram data retaining voltage v ram v cc 1.5 ? ? v
rev. 4.00, 03/04, page 356 of 462 table 17.2 dc characteristics (6) v cc = 1.8 v to 5.5 v, av cc = 1.8 v to 5.5 v, v ss =av ss = 0.0 v, unless otherwise specified (including subactive mode), t a = ?20c to +75c (product with regular specifications), t a =? 40c to +85c (product with wide-range temperature specifications), t a = +75c (bare die product) values item symbol applicable pins test condition min typ max unit notes allowable output low current (per pin) i ol output pins except ports 3 and 9 v cc =4.0vto 5.5 v ??2.0ma port 3 v cc =4.0vto 5.5 v ? ? 10.0 output pins except port 9 ??0.5 p90 to p92 v cc =2.2vto 5.5 v ? ? 25.0 * 5 ? ? 15.0 ? ? 10.0 p93 to p95 ? ? 10.0 allowable output low current (total) i ol output pins except ports 3 and 9 v cc =4.0vto 5.5 v ? ? 40.0 ma port 3 v cc =4.0vto 5.5 v ? ? 80.0 output pins except port 9 ? ? 20.0 port 9 ? ? 80.0 ?i oh all output pins v cc =4.0vto 5.5 v ??2.0ma allowable output high current (per pin) other than above ??0.2 ?i oh all output pins v cc =4.0vto 5.5 v ? ? 15.0 ma allowable output high current (total) other than above ? ? 10.0 notes: 1. applies to the mask-rom version. 2. applies to the hd6473802. 3. pin states when current consumption is measured
rev. 4.00, 03/04, page 357 of 462 mode res res res res pin internal state other pins lcd power supply oscillator pins active (high-speed) mode (i ope1 ) active (medium- speed) mode (i ope2 ) v cc only cpu operates v cc stops sleep mode v cc only timers operate v cc stops system clock: crystal resonator subclock: pinx1=gnd subactive mode v cc only cpu operates v cc stops subsleep mode v cc only timers operate cpu stops v cc stops watch mode v cc only clock time base operates cpu stops v cc stops system clock: crystal resonator subclock: crystal resonator standby mode v cc cpu and timers both stop v cc stops system clock: crystal resonator subclock: pinx1=gnd notes: 4. except current which flows to the pull-up mos or output buffer 5. when the pioff bit in the port mode register 9 is 0 6. when the pioff bit in the port mode register 9 is 1
rev. 4.00, 03/04, page 358 of 462 17.2.3 ac characteristics table 17.3 lists the control signal timing and table 17.4 lists the serial interface timing. table 17.3 control signal timing v cc = 1.8 v to 5.5 v, av cc = 1.8 v to 5.5 v, v ss =av ss = 0.0 v, unless otherwise specified (including subactive mode), t a = ?20c to +75c (product with regular specifications), t a =? 40c to +85c (product with wide-range temperature specifications), t a = +75c (bare die product) a pp licable values reference item symbol pins test condition min typ max unit figure system clock oscillation f osc osc1, osc2 v cc = 4.5 v to 5.5 v 2.0 ? 16.0 mhz frequency v cc = 2.7 v to 5.5 v 2.0 ? 10.0 other than above 2.0 ? 4.0 500 v cc = 4.5 v to 5.5 v 62.5 ? (1000) 500 v cc = 2.7 v to 5.5 v 100 ? (1000) 500 osc clock ( osc ) cycle time t osc osc1, osc2 other than above 250 ? (1000) ns figure 17.1 * 2 system clock ( )t cyc 2 ? 128 t osc cycle time ? ? 128 s subclock oscillation frequency f w x1, x2 ? 32.768 or 38.4 ?khz watch clock ( w ) cycle time t w x1, x2 ? 30.5 or 26.0 ? s figure 17.1 subclock ( sub ) cycle time t subcyc 2? 8 t w * 1 instruction cycle time 2? ?t cyc t subcyc t rc osc1, osc2 v cc = 2.2 v to 5.5 v in figure 17.7 ? 20 45 s figure 17.7 oscillation stabilization time other than above ? ? 50 ms x1, x2 v cc = 2.7 v to 5.5 v ? ? 2.0 s * 3 v cc = 2.2 v to 5.5 v ? ? 10.0
rev. 4.00, 03/04, page 359 of 462 a pp licable values reference item symbol pins test condition min typ max unit figure external clock t cph osc1 v cc = 4.5 v to 5.5 v 25 ? ? ns figure 17.1 high width v cc = 2.7 v to 5.5 v 40 ? ? other than above 100 ? ? x1 ? 15.26 or 13.02 ?s external clock t cpl osc1 v cc = 4.5 v to 5.5 v 25 ? ? ns figure 17.1 low width v cc = 2.7 v to 5.5 v 40 ? ? other than above 100 ? ? x1 ? 15.26 or 13.02 ?s external clock t cpr osc1 v cc = 4.5 v to 5.5 v ? ? 6 ns figure 17.1 rise time v cc = 2.7 v to 5.5 v ? ? 10 other than above ? ? 25 x1 ? ? 55.0 ns external clock t cpf osc 1 v cc = 4.5 v to 5.5 v ? ? 6 ns figure 17.1 fall time v cc = 2.7 v to 5.5 v ? ? 10 other than above ? ? 25 x1 ? ? 55.0 ns res pin low width t rel res 10 ? ? t cyc figure 17.2 input pin high width t ih irq0 , irq1 , irqaec, wkp0 to wkp7 , 2? ?t cyc t subcyc figure 17.3 aevl, aevh 0.5 ? ? t osc input pin low width t il irq0 , irq1 , irqaec, wkp0 to wkp7 , 2? ?t cyc t subcyc figure 17.3 aevl, aevh 0.5 ? ? t osc notes: 1. determined by the sa1 and sa0 bits in the system control register 2 (syscr2). 2. values in parentheses indicate t osc max. when the external clock is used. 3. after powering on, hold v cc at 2.2 v to 5.5 v until the oscillation stabilization time has elapsed.
rev. 4.00, 03/04, page 360 of 462 table 17.4 serial interface (sci3) timing v cc = 1.8 v to 5.5 v, av cc = 1.8 v to 5.5 v, v ss =av ss = 0.0 v, unless otherwise specified (including subactive mode), t a = ?20c to +75c (product with regular specifications), t a =? 40c to +85c (product with wide-range temperature specifications), t a = +75c (bare die product) values reference item symbol test condition min typ max unit figure input clock asynchronous t scyc 4??t cyc or t subcyc figure 17.4 cycle clocked synchronous 6?? input clock pulse width t sckw 0.4 ? 0.6 t scyc figure 17.4 t txd v cc = 4.0 v to 5.5 v ? ? 1 t cyc or t subcyc figure 17.5 transmit data delay time (clocked synchronous) other than above ? ? 1 t rxs v cc = 4.0 v to 5.5 v 200.0 ? ? ns figure 17.5 receive data setup time (clocked synchronous) other than above 400.0 ? ? t rxh v cc = 4.0 v to 5.5 v 200.0 ? ? ns figure 17.5 receive data hold time (clocked synchronous) other than above 400.0 ? ? 17.2.4 a/d converter characteristics table 17.5 shows the a/d converter characteristics. table 17.5 a/d converter characteristics v cc = 1.8 v to 5.5 v, v ss =av ss =0.0v,t a = ?20c to +75c (product with regular specifications), t a = ?40c to +85c (product with wide-range temperature specifications), t a = +75c (bare die product), unless otherwise specified a pp licable test values reference item symbol pins condition min typ max unit figure analog power supply voltage av cc av cc 1.8 ? 5.5 v * 1 analog input voltage av in an0 to an3 ?0.3 ? av cc +0.3 v analog power supply current ai ope av cc av cc = 5.0 v ? ? 1.5 ma ai stop1 av cc ? 600 ? a * 2 reference value ai stop2 av cc ??5.0a * 3
rev. 4.00, 03/04, page 361 of 462 a pp licable test values reference item symbol pins condition min typ max unit figure analog input capacitance c ain an0 to an3 ? ? 15.0 pf allowable signal source impedance r ain ? ? 10.0 k ? resolution (data length) ? ? 10 bit nonlinearity error av cc =2.7v to 5.5 v v cc =2.7vto 5.5 v ??2.5lsb av cc =2.0v to 5.5 v v cc =2.0vto 5.5 v ??5.5 other than above ??7.5 * 4 quantization error ? ? 0.5 lsb absolute accuracy av cc =2.7v to 5.5 v v cc =2.7vto 5.5 v ??3.0lsb av cc =2.0v to 5.5 v v cc =2.0vto 5.5 v ??6.0 other than above ??8.0 * 4 conversion time av cc =2.7v to 5.5 v v cc =2.7vto 5.5 v 12.4 ? 124 s other than above 62 ? 124 notes: 1. set av cc =v cc when the a/d converter is not used. 2. ai stop1 is the current in active and sleep modes while the a/d converter is idle. 3. ai stop2 is the current at reset and in standby, watch, subactive, and subsleep modes while the a/d converter is idle. 4. the conversion time is 62 s.
rev. 4.00, 03/04, page 362 of 462 17.2.5 lcd characteristics table 17.6 shows the lcd characteristics. table 17.6 lcd characteristics v cc = 1.8 v to 5.5 v, av cc = 1.8 v to 5.5 v, v ss =av ss = 0.0 v, unless otherwise specified (including subactive mode), t a = ?20c to +75c (product with regular specifications), t a =? 40c to +85c (product with wide-range temperature specifications), t a = +75c (bare die product) applicable values reference item symbol pins test condition min typ max unit figure segment driver step-down voltage v ds seg1 to seg25 i d =2a v1 = 2.7 v to 5.5 v ??0.6v * 1 common driver step-down voltage v dc com1 to com4 i d =2a v1 = 2.7 v to 5.5 v ??0.3v * 1 lcd power supply split-resistance r lcd between v1 and v ss 0.5 3.0 9.0 m ? liquid crystal display voltage v lcd v1 2.2 ? 5.5 v * 2 notes: 1. the voltage step-down from power supply pins v1, v2, v3, and v ss to each segment pinorcommonpin. 2. when the liquid crystal display voltage is supplied from an external power supply, ensure that the following relationship is maintained: v cc v1 v2 v3 v ss .
rev. 4.00, 03/04, page 363 of 462 17.3 absolute maximum ratings of h8/38004 group table 17.7 lists the absolute maximum ratings. table 17.7 absolute maximum ratings item symbol value unit note power supply voltage v cc ?0.3 to +4.3 v * 1 analog power supply voltage av cc ?0.3 to +4.3 v input voltage other than port b v in ?0.3tov cc +0.3 v port b av in ?0.3toav cc +0.3 v port 9 pin voltage v p9 ?0.3tov cc +0.3 v operating temperature t opr regular specifications: ?20 to +75 * 2 c wide-range temperature specifications: ?40 to +85 * 3 bare die product: +75 * 4 storage temperature t stg ?55 to +125 c notes: 1. permanent damage may result if maximum ratings are exceeded. normal operation should be under the conditions specified in electrical characteristics. exceeding these values can result in incorrect operation and reduced reliability. 2. when the operating voltage is v cc = 2.7 to 3.6 v during flash memory reading, the operating temperature ranges from ?20 cto+75 c when programming or erasing the flash memory. when the operating voltage is v cc = 2.2 to 3.6 v during flash memory reading, the operating temperature ranges from ?20 cto+50 c when programming or erasing the flash memory. 3. the operating temperature ranges from ?20 cto+75 c when programming or erasing the flash memory. 4. the current-carrying temperature ranges from ?20 cto+75 c.
rev. 4.00, 03/04, page 364 of 462 17.4 electrical characteristics of h8/38004 group 17.4.1 power supply voltage and operating ranges power supply voltage and oscillation frequency range (f-ztat version) 10.0 38.4 32.768 4.0 2.0 2.2 2.7 3.6 2.2 2.7 3.6 fw(khz) fosc(m hz) vcc (v) vcc (v) active (high-speed) mode sleep (high-speed) mode all operating modes power supply voltage and oscillation frequency range (mask rom version) 10.0 38.4 32.768 4.0 2.0 1.8 2.7 3.6 1.8 2.7 3.6 fw(khz) fosc(mhz) vcc (v) vcc (v) active (high-speed) mode sleep (high-speed) mode all operating modes when a resonator is used, hold vcc at 2.2 v to 3.6 v from power-on until the oscillation stabilization time has elapsed.
rev. 4.00, 03/04, page 365 of 462 power supply voltage and operating frequency range (f-ztat version) 5.0 19.2 16.384 9.6 8.192 4.8 4.096 2.0 1.0 2.2 2.7 3.6 2.2 2.7 3.6 (khz) (mhz) vcc (v) vcc (v) active (high-speed) mode sleep (high-speed) mode (except cpu) 625 250 15.625 2.2 2.7 3.6 (khz) vcc (v) active (medium-speed) mode slee p ( medium-s p eed ) mode ( exce p t a/d converter ) subactive mode subsleep mode (except cpu) watch mode (except cpu) sub
rev. 4.00, 03/04, page 366 of 462 power supply voltage and operating frequency range (mask rom version) 5.0 19.2 16.384 9.6 8.192 4.8 4.096 2.0 1.0 1.8 2.7 3.6 1.8 2.7 3.6 (kh z) (m hz) vcc (v) vcc (v) active (high-speed) mode sleep (high-speed) mode (except cpu) 625 250 15.625 1.8 2.7 3.6 (khz) vcc (v) active (medium-speed) mode sleep (medium-speed) mode (except a/d converter) subactive mode subsleep mode (except cpu) watch mode (except cpu) sub
rev. 4.00, 03/04, page 367 of 462 analog power supply voltage and a/d converter operating range (f-ztat version) 5.0 625 500 1.0 2.2 2.7 3.6 2.7 3.6 (khz) (m hz) avcc (v) avcc (v) active (high-speed) mode sleep (high-speed) mode note: when avcc = 2.2 v to 2.7 v, the operating range is limited to = 1.0 mhz. active (medium-speed) mode sleep (medium-speed) mode analog power supply voltage and a/d converter operating range (mask rom version) 5.0 625 500 1.0 1.8 2.7 3.6 2.7 3.6 (khz) (m hz) avcc (v) avcc (v) active (high-speed) mode sleep (high-speed) mode note: when avcc = 1.8 v to 2.7 v, the operating range is limited to = 1.0 mhz. active (medium-speed) mode sleep (medium-speed) mode
rev. 4.00, 03/04, page 368 of 462 17.4.2 dc characteristics table 17.8 lists the dc characteristics. table 17.8 dc characteristics one of following conditions is applied unless otherwise specified. condition a (f-ztat version): v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ss =av ss =0.0v condition b (f-ztat version): v cc = 2.2 v to 3.6 v, av cc = 2.2 v to 3.6 v, v ss =av ss =0.0v condition c (mask rom version): v cc = 1.8 v to 3.6 v, av cc = 1.8 v to 3.6 v, v ss =av ss =0.0v values item symbol applicable pins test condition min typ max unit notes input high voltage v ih res , wkp0 to wkp7 , irq0 , irq1, aevl, aevh, sck32 v cc 0.9 ? v cc +0.3 v rxd32 v cc 0.8 ? v cc +0.3 v osc1 v cc 0.9 ? v cc +0.3 v x1 v cc = 1.8 v to 5.5 v v cc 0.9 ? v cc +0.3 v p31 to p37, p40 to p43, p50 to p57, p60 to p67, p70 to p77, p80, pa0 to pa3 v cc 0.8 ? v cc +0.3 v pb0 to pb3 v cc 0.8 ? av cc + 0.3 v irqaec, p95 * 5 v cc 0.9 ? v cc +0.3 v input low voltage v il res , wkp0 to w kp 7 , irq0 , irq1, irqaec, aevl, aevh, sck32 ?0.3 ? v cc 0.1 v rxd32 ?0.3 ? v cc 0.2 v osc1 ? 0.3 ? v cc 0.1 v
rev. 4.00, 03/04, page 369 of 462 values item symbol applicable pins test condition min typ max unit notes x1 ? 0.3 ? v cc 0.1 v input low voltage p31 to p37, p40 to p43, p50 to p57, p60 to p67, p70 to p77, p80, pa0 to pa3, pb0 to pb3 ?0.3 ? v cc 0.2 v v oh v cc = 2.7 v to 3.6 v ?i oh =1.0ma v cc ? 1.0 ?? v output high voltage p31 to p37, p40 to p42, p50 to p57, p60 to p67, p70 to p77, p80, pa0 to pa3 ?i oh =0.1ma v cc ? 0.3 ?? output low voltage v ol p40 to p42, p50 to p57, p60 to p67, p70 to p77, p80, pa0 to pa3, p31 to p37 i ol =0.4ma ? ? 0.5 v p90 to p95 v cc = 2.2 v to 3.6 v i ol = 10.0 ma ??0.5 v cc = 1.8 v to 3.6 v i ol =8.0ma input/ output leakage current |i il | res ,p43, osc1, x1, p31 to p37, p40 to p42, p50 to p57, p60 to p67, p70 to p77, p80, irqaec, pa0 to pa3, p90 to p95 v in =0.5vtov cc ? 0.5 v ??1.0 a pb0 to pb3 v in =0.5vtoav cc ?0.5v ??1.0 pull-up mos current ?i p p31 to p37, p50 to p57, p60 to p67 v cc =3.0v, v in =0.0v 30 ? 180 a input capaci- tance c in all input pins except power supply pin f=1mhz, v in =0.0v, t a =25c ? ? 15.0 pf
rev. 4.00, 03/04, page 370 of 462 values item symbol applicable pins test condition min typ max unit notes active (high-speed) mode v cc =1.8v, f osc =2mhz ?0.4?ma * 1 * 3 * 4 approx. max. value =1.1 typ. i ope1 v cc active (high-speed) mode v cc =3v, f osc =2mhz ?0.6? * 1 * 3 * 4 approx. max. value =1.1 typ. ?1.0? * 2 * 3 * 4 approx. max. value =1.1 typ. active (high-speed) mode v cc =3v, f osc =4mhz ?1.2? * 1 * 3 * 4 approx. max. value =1.1 typ. ?1.62.8 * 2 * 3 * 4 condition b ?3.16.0 * 1 * 3 * 4 active (high-speed) mode v cc =3v, f osc =10mhz ?3.66.0 * 2 * 3 * 4 condition a active (medium- speed) mode v cc =1.8v, f osc =2mhz, osc /128 ?0.06?ma * 1 * 3 * 4 approx. max. value =1.1 typ. active mode current consump- tion i ope2 v cc active (medium- speed) mode v cc =3v, f osc =2mhz, osc /128 ?0.1? * 1 * 3 * 4 approx. max. value =1.1 typ. ?0.5? * 2 * 3 * 4 approx. max. value =1.1 typ.
rev. 4.00, 03/04, page 371 of 462 values item symbol applicable pins test condition min typ max unit notes active mode current consump- tion i ope2 v cc active (medium- speed) mode v cc =3v, f osc =4mhz, osc /128 ?0.2? * 1 * 3 * 4 approx. max. value =1.1 typ. ?0.71.3 * 2 * 3 * 4 condition b ?0.61.8 * 1 * 3 * 4 active (medium- speed) mode v cc =3v, f osc =10mhz, osc /128 ?1.01.8 * 2 * 3 * 4 condition a v cc =1.8v, f osc =2mhz ?0.16?ma * 1 * 3 * 4 approx. max. value =1.1 typ. sleep mode current consump- tion i sleep v cc v cc =3v, f osc =2mhz ?0.3? * 1 * 3 * 4 approx. max. value =1.1 typ. ?0.6? * 2 * 3 * 4 approx. max. value =1.1 typ. v cc =3v, f osc =4mhz ?0.5? * 1 * 3 * 4 approx. max. value =1.1 typ. ?0.92.2 * 2 * 3 * 4 condition b ?1.34.8 * 1 * 3 * 4 v cc =3v, f osc =10mhz ?1.74.8 * 2 * 3 * 4 condition a
rev. 4.00, 03/04, page 372 of 462 values item symbol applicable pins test condition min typ max unit notes v cc =1.8v, lcd on, 32-khz crystal resonator used ( sub = w /2) ?6.2?a * 1 * 3 * 4 reference value ?4.4? * 1 * 3 * 4 reference value v cc =2.7v, lcd on, 32-khz crystal resonator used ( sub = w /8) ?8.0? * 2 * 3 * 4 reference value ?1040 * 1 * 3 * 4 subactive mode current consump- tion i sub v cc v cc =2.7v, lcd on, 32-khz crystal resonator used ( sub = w /2) ?2850 * 2 * 3 * 4 subsleep mode current consump- tion i subsp v cc v cc =2.7v, lcd on, 32-khz crystal resonator used ( sub = w /2) ?4.616a * 3 * 4 watch mode current consump- tion i watch v cc v cc =1.8v, ta = 25 c, 32-khz crystal resonator used, lcd not used ?1.2?a * 1 * 3 * 4 reference value v cc =2.7v, ta = 25 c, 32-khz crystal resonator used, lcd not used ?2.0? * 3 * 4 reference value v cc =2.7v, 32-khz crystal resonator used, lcd not used ?2.06.0 * 3 * 4 i stby v cc v cc =1.8v, ta = 25 c, 32-khz crystal resonator not used ?0.1?a * 1 * 3 * 4 reference value standby mode current consump- tion v cc =3.0v, ta = 25 c, 32-khz crystal resonator not used ?0.3? * 3 * 4 reference value 32-khz crystal resonator not used ?1.05.0 * 3 * 4
rev. 4.00, 03/04, page 373 of 462 values item symbol applicable pins test condition min typ max unit notes ram data retaining voltage v ram v cc 1.5 ? ? v i ol output pins except port 9 ??0.5ma p90 to p95 v cc = 2.2 v to 3.6 v ? ? 10.0 allowable output low current (per pin) other than above ? ? 8.0 i ol output pins except port 9 ? ? 20.0 ma allowable output low current (total) port 9 ? ? 60.0 ?i oh all output pins v c c = 2.7 v to 3.6 v ? ? 2.0 ma allowable output high current (per pin) other than above ? ? 0.2 allowable output high current (total) ?i oh all output pins ? ? 10.0 ma notes: connect the test pin to v ss . 1. applies to the mask-rom version. 2. applies to the f-ztat version. 3. pin states when current consumption is measured
rev. 4.00, 03/04, page 374 of 462 mode res res res res pin internal state other pins lcd power supply oscillator pins active (high-speed) mode (i ope1 ) active (medium- speed) mode (i ope2 ) v cc only cpu operates v cc stops sleep mode v cc only all on-chip timers operate v cc stops system clock: crystal resonator subclock: pin x 1 =gnd subactive mode v cc only cpu operates v cc stops subsleep mode v cc only all on-chip timers operate cpu stops v cc stops watch mode v cc only clock time base operates cpu stops v cc stops system clock: crystal resonator subclock: crystal resonator standby mode v cc cpu and timers both stop v cc stops system clock: crystal resonator subclock: pin x 1 =gnd notes: 4. except current which flows to the pull-up mos or output buffer 5. used when user mode or boot mode is determined after canceling a reset in the f- ztat version
rev. 4.00, 03/04, page 375 of 462 17.4.3 ac characteristics table 17.9 lists the control signal timing and table 17.10 lists the serial interface timing. table 17.9 control signal timing one of following conditions is applied unless otherwise specified. condition a (f-ztat version): v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ss =av ss =0.0v condition b (f-ztat version): v cc = 2.2 v to 3.6 v, av cc = 2.2 v to 3.6 v, v ss =av ss =0.0v condition c (mask rom version): v cc = 1.8 v to 3.6 v, av cc = 1.8 v to 3.6 v, v ss =av ss =0.0v applicable values reference item symbol pins test condition min typ max unit figure system clock oscillation frequency f osc osc1, osc2 v cc = 2.7 v to 3.6 v in conditions a and c 2.0 ? 10.0 mhz other than above in condition c and condition b 2.0 ? 4.0 osc clock ( osc ) cycle time t osc osc1, osc2 v cc = 2.7 v to 3.6 v in conditions a and c 100 ? 500 ns figure 17.1 other than above in condition c and condition b 250 ? 500 system clock ( )t cyc 2 ? 128 t osc cycle time ?? 64 s subclock oscillation frequency f w x1, x2 ? 32.768 or 38.4 ?khz watch clock ( w ) cycle time t w x1, x2 ? 30.5 or 26.0 ? s figure 17.1 subclock ( sub ) cycle time t subcyc 2? 8 t w * instruction cycle time 2? ? t cyc t subcyc
rev. 4.00, 03/04, page 376 of 462 applicable values reference item symbol pins test condition min typ max unit figure oscillation stabilization time t rc osc1, osc2 v cc = 2.7 v to 3.6 v when using crystal resonator in figure 17.8 ? 0.8 2.0 ms figure 17.8 v cc = 2.2 v to 3.6 v when using crystal resonator in figure 17.8 and in conditions b and c ?1.2 3.0 other than above in condition c and when using crystal resonator in figure 17.8 ?4.0 ? v cc = 2.7 v to 3.6 v when using ceramic resonator in figure 17.8 and in conditions a and c ?20 45 s v cc = 2.2 v to 3.6 v when using ceramic resonator (1)infigure17.8 and in conditions b and c ?20 45 other than above in condition c and when using ceramic resonator (1) in figure 17.8 ?80 ? other than above ? ? 50 ms t rc x1, x2 v cc = 2.7 v to 3.6 v ?? 2.0 s v cc = 2.2 v to 3.6 v and in conditions b and c ?? 2.0 other than above in condition c ?4.0 ? external clock high width t cph osc1 v cc = 2.7 v to 3.6 v in conditions a and c 40 ? ? ns figure 17.1 other than above in condition c and condition b 100 ? ? x1 ? 15.26 or 13.02 ?s
rev. 4.00, 03/04, page 377 of 462 applicable values reference item symbol pins test condition min typ max unit figure external clock low width t cpl osc1 v cc = 2.7 v to 3.6 v in conditions a and c 40 ? ? ns figure 17.1 other than above in condition c and condition b 100 ? ? x1 ? 15.26 or 13.02 ?s external clock rise time t cpr osc1 v cc = 2.7 v to 3.6 v in conditions a and c ? ? 10 ns figure 17.1 other than above in condition c and condition b ?? 25 x1 ? ? 55.0 ns external clock fall time t cpf osc1 v cc = 2.7 v to 3.6 v in conditions a and c ? ? 10 ns figure 17.1 other than above in condition c and condition b ?? 25 x1 ? ? 55.0 ns res pin low width t rel res 10 ? ? t cyc figure 17.2 input pin high width t ih irq0 , irq1 , irqaec, wkp0 to wkp7 , 2? ? t cyc t subcyc figure 17.3 aevl, aevh 0.5 ? ? t osc input pin low width t il irq0 , irq1 , irqaec, wkp0 to wkp7 , 2 ??t cyc t subcyc figure 17.3 aevl, aevh 0.5 ? ? t osc note: * determined by the sa1 and sa0 bits in the system control register 2 (syscr2).
rev. 4.00, 03/04, page 378 of 462 table 17.10 serial interface (sci3) timing one of following conditions is applied unless otherwise specified. condition a (f-ztat version): v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ss =av ss =0.0v condition b (f-ztat version): v cc = 2.2 v to 3.6 v, av cc = 2.2 v to 3.6 v, v ss =av ss =0.0v condition c (mask rom version): v cc = 1.8 v to 3.6 v, av cc = 1.8 v to 3.6 v, v ss =av ss =0.0v values item symbol test condition min typ max unit reference figure asynchronous t scyc 4 ??t cyc or t subcyc figure 17.4 input clock cycle clocked synchronous 6 ? ? input clock pulse width t sckw 0.4 ? 0.6 t scyc figure 17.4 transmit data delay time (clocked synchronous) t txd ??1t cyc or t subcyc figure 17.5 receive data setup time (clocked synchronous) t rxs 400.0 ? ? ns figure 17.5 receive data hold time (clocked synchronous) t rxh 400.0 ? ? ns figure 17.5
rev. 4.00, 03/04, page 379 of 462 17.4.4 a/d converter characteristics table 17.11 shows the a/d converter characteristics. table 17.11 a/d converter characteristics one of following conditions is applied unless otherwise specified. condition a (f-ztat version): v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ss =av ss =0.0v condition b (f-ztat version): v cc = 2.2 v to 3.6 v, av cc = 2.2 v to 3.6 v, v ss =av ss =0.0v condition c (mask rom version): v cc = 1.8 v to 3.6 v, av cc = 1.8 v to 3.6 v, v ss =av ss =0.0v a pp licable test values reference item symbol pins condition min typ max unit figure av cc av cc condition a 2.7 ? 3.6 v * 1 analog power supply voltage condition b 2.2 ? 3.6 condition c 1.8 ? 3.6 analog input voltage av in an0 to an3 ?0.3 ? av cc +0.3 v ai ope av cc av cc = 3.0 v ? ? 1.0 ma analog power supply current ai stop1 av cc ? 600 ? a * 2 reference value ai stop2 av cc ??5.0 a * 3 analog input capacitance c ain an0 to an3 ? ? 15.0 pf allowable signal source impedance r ain ? ? 10.0 k ? resolution (data length) ? ? 10 bit
rev. 4.00, 03/04, page 380 of 462 a pp licable test values reference item symbol pins condition min typ max unit figure nonlinearity error av cc =2.7v to 3.6 v ??3.5 lsb av cc =2.2v to 3.6 v in condition b, av cc =2.0v to 3.6 v in condition c ??5.5 other than above in condition c ??7.5 * 4 quantization error ? ? 0.5 lsb absolute accuracy av cc =2.7v to 3.6 v ? 2.0 4.0 lsb av cc =2.2v to 3.6 v in condition b, av cc =2.0v to 3.6 v in condition c ? 2.5 6.0 other than above in condition c ? 2.5 8.0 * 4 conversion time av cc =2.7v to 3.6 v 12.4 ? 124 s other than above 62 ? 124 notes: 1. set av cc =v cc when the a/d converter is not used. 2. ai stop1 is the current in active and sleep modes while the a/d converter is idle. 3. ai stop2 is the current at reset and in standby, watch, subactive, and subsleep modes while the a/d converter is idle. 4. the conversion time is 62 s.
rev. 4.00, 03/04, page 381 of 462 17.4.5 lcd characteristics table 17.12 shows the lcd characteristics. table 17.12 lcd characteristics one of following conditions is applied unless otherwise specified. condition a (f-ztat version): v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ss =av ss =0.0v condition b (f-ztat version): v cc = 2.2 v to 3.6 v, av cc = 2.2 v to 3.6 v, v ss =av ss =0.0v condition c (mask rom version): v cc = 1.8 v to 3.6 v, av cc = 1.8 v to 3.6 v, v ss =av ss =0.0v applicable values reference item symbol pins test condition min typ max unit figure segment driver step-down voltage v ds seg1 to seg25 i d =2a v1 = 2.7 v to 3.6 v ??0.6v * 1 common driver step-down voltage v dc com1 to com4 i d =2a v1 = 2.7 v to 3.6 v ??0.3v * 1 lcd power supply split-resistance r lcd between v1 and v ss 1.5 3.0 7.0 m ? liquid crystal display voltage v lcd v1 2.2 ? 3.6 v * 2 notes: 1. the voltage step-down from power supply pins v1, v2, v3, and v ss to each segment pinorcommonpin. 2. when the liquid crystal display voltage is supplied from an external power supply, ensure that the following relationship is maintained: v cc v1 v2 v3 v ss .
rev. 4.00, 03/04, page 382 of 462 17.4.6 flash memory characteristics table 17.13 flash memory characteristics condition a: av cc = 2.7 v to 3.6 v, v ss =av ss =0.0v,v cc = 2.7 v to 3.6 v (range of operating voltage when reading), v cc = 3.0 v to 3.6 v (range of operating voltage when programming/erasing), t a = ?20c to +75c (range of operating temperature when programming/erasing: product with regular specifications, product with wide-range temperature specifications, bare die product) condition b: av cc = 2.2 v to 3.6 v, v ss =av ss =0.0v,v cc =2.2vto3.6v(rangeof operating voltage when reading), v cc = 3.0 v to 3.6 v (range of operating voltage when programming/erasing), t a = ?20c to +50c (range of operating temperature when programming/erasing: product with regular specifications) values item symbol test conditions min typ max unit programming time * 1 * 2 * 4 t p ? 7 200 ms/ 128 bytes erase time * 1 * 3 * 5 t e ? 100 1200 ms/ block reprogramming count n wec 1000 * 8 10000 * 9 ?times data retain period t drp 10 * 10 ? ? year programming wait time after swe-bit setting * 1 x1??s wait time after psu-bit setting * 1 y50??s z1 1 n 6283032s z2 7 n 1000 198 200 202 s wait time after p-bit setting * 1 * 4 z3 additional programming 81012s wait time after p-bit clear * 1 5??s wait time after psu-bit clear * 1 5??s wait time after pv-bit setting * 1 4??s wait time after dummy write * 1 2??s wait time after pv-bit clear * 1 2??s wait time after swe-bit clear * 1 100 ? ? s
rev. 4.00, 03/04, page 383 of 462 values item symbol test conditions min typ max unit programming maximum programming count * 1 * 4 * 5 n ? ? 1000 times wait time after swe-bit setting * 1 x1??s wait time after esu-bit setting * 1 y 100 ? ? s wait time after e-bit setting * 1 * 6 z 10 ? 100 ms wait time after e-bit clear * 1 10 ? ? s wait time after esu-bit clear * 1 10 ? ? s wait time after ev-bit setting * 1 20 ? ? s wait time after dummy write * 1 2??s wait time after ev-bit clear * 1 4??s wait time after swe-bit clear * 1 100 ? ? s erase maximum erase count * 1 * 6 * 7 n ? ? 120 times notes: 1. set the times according to the program/erase algorithms. 2. programming time per 128 bytes (shows the total period for which the p bit in flmcr1 is set. it does not include the programming verification time.) 3. block erase time (shows the total period for which the e bit in flmcr1 is set. it does not include the erase verification time.) 4. maximum programming time (t p (max)) t p (max) = wait time after p-bit setting (z) maximum number of writes (n) 5. the maximum number of writes (n) should be set according to the actual set value of z1, z2, and z3 to allow programming within the maximum programming time (t p (max)). the wait time after p-bit setting (z1 and z2) should be alternated according to the number of writes (n) as follows: 1 n 6z1=30s 7 n 1000 z2 = 200 s 6. maximum erase time (t e (max)) t e (max) = wait time after e-bit setting (z) maximum erase count (n) 7. the maximum number of erases (n) should be set according to the actual set value of z to allow erasing within the maximum erase time (t e (max)). 8. this minimum value guarantees all characteristics after reprogramming (the guaranteed range is from 1 to the minimum value). 9. reference value when the temperature is 25 c (normally reprogramming will be performed by this count). 10. this is a data retain characteristic when reprogramming is performed within the specification range including this minimum value.
rev. 4.00, 03/04, page 384 of 462 17.5 absolute maximum ratings of h8/38104 group table 17.14 lists the absolute maximum ratings. table 17.14 absolute maximum ratings item symbol value unit note power supply voltage v cc ?0.3 to +7.0 v * 1 cv cc ?0.3 to +4.3 v analog power supply voltage av cc ?0.3 to +7.0 v input voltage other than port b v in ?0.3tov cc +0.3 v port b av in ?0.3toav cc +0.3 v port 9 pin voltage v p9 ?0.3tov cc +0.3 v operating temperature t opr regular specifications: ?20 to +75 * 2 c wide-range temperature specifications: ?40 to +85 * 2 storage temperature t stg ?55 to +125 c notes: 1. permanent damage may result if maximum ratings are exceeded. normal operation should be under the conditions specified in electrical characteristics. exceeding these values can result in incorrect operation and reduced reliability. 2. the operating temperature ranges from ?20 cto+75 c when programming or erasing the flash memory.
rev. 4.00, 03/04, page 385 of 462 17.6 electrical characteristics of h8/38104 group 17.6.1 power supply voltage and operating ranges power supply voltage and oscillation frequency range (system clock oscillator selected) 5.5 v cc (v) f w (khz) all operating modes 32.768 2.7 2.0 16.0 2.7 5.5 v cc (v) fosc (mhz) active (high-speed) mode sleep (high-speed) mode power supply voltage and oscillation frequency range (on-chip oscillator selected) 5.5 v cc (v) f w (khz) ? all operating modes 32.768 2.7 0.8 2.0 2.7 5.5 v cc (v) fosc (mhz) active (high-speed) mode sleep (high-speed) mode
rev. 4.00, 03/04, page 386 of 462 power supply voltage and operating frequency range (system clock oscillator selected) subactive mode subsleep mode (except cpu) watch mode (except cpu) 16.384 8.192 4.096 2.7 5.5 v cc (v) sub (khz) 8.0 1.0 2.7 5.5 v cc (v) (mhz) active (high-speed) mode sleep (high-speed) mode (except cpu) 1000 15.625 2.7 5.5 v cc (v) (khz) active (medium-speed) mode sleep (medium-speed) mode (except a/d converter)
rev. 4.00, 03/04, page 387 of 462 power supply voltage and operating frequency range (on-chip oscillator selected) subactive mode subsleep mode (except cpu) watch mode (except cpu) 16.384 8.192 4.096 2.7 5.5 v cc (v) sub (khz) 1.0 0.4 2.7 5.5 v cc (v) (mhz) active (high-speed) mode sleep (high-speed) mode (except cpu) 125 6.25 2.7 5.5 v cc (v) (khz) active (medium-speed) mode sleep (medium-speed) mode (except a/d converter)
rev. 4.00, 03/04, page 388 of 462 analog power supply voltage and a/d converter operating range (system clock oscillator selected) 5.0 1.0 2.7 5.5 av cc (v) (mhz) active (high-speed) mode sleep (high-speed) mode 625 500 2.7 5.5 av cc (v) (khz) active (medium-speed) mode sleep (medium-speed) mode analog power supply voltage and a/d converter operating range (on-chip oscillator selected) 1.0 0.4 2.7 5.5 av cc (v) (mhz) active (high-speed) mode sleep (high-speed) mode 125 6.25 2.7 5.5 av cc (v) (khz) active (medium-speed) mode sleep (medium-speed) mode
rev. 4.00, 03/04, page 389 of 462 17.6.2 dc characteristics table 17.15 lists the dc characteristics. table 17.15 dc characteristics (1) v cc = 2.7 v to 5.5 v, av cc = 2.7 v to 5.5 v, v ss =av ss = 0.0 v, unless otherwise specified values item symbol applicable pins test condition min typ max unit notes input high voltage v ih res , wkp0 to wkp7 , irq0 , irq1, aevl, aevh, v cc = 4.0 v to 5.5 v v cc 0.8 ? v cc +0.3 v sck32 other than above v cc 0.9 ? v cc +0.3 rxd32 v cc = 4.0 v to 5.5 v v cc 0.7 ? v cc +0.3 v other than above v cc 0.8 ? v cc +0.3 osc 1 v cc = 4.0 v to 5.5 v v cc 0.8 ? v cc +0.3 v other than above v cc 0.9 ? v cc +0.3 p31 to p37, p40 to p43, p50 to p57, v cc = 4.0 v to 5.5 v v cc 0.7 ? v cc +0.3 v p60 to p67, p70 to p77, p80, pa0 to pa3 other than above v cc 0.8 ? v cc +0.3 pb0 to pb3 v cc = 4.0 v to 5.5 v v cc 0.7 ? av cc +0.3 v other than above v cc 0.8 ? av cc +0.3 irqaec, p95 * 5 v cc = 4.0 v to 5.5 v v cc 0.8 ? v cc +0.3 v other than above v cc 0.9 ? v cc +0.3 note: connect the test pin to v ss .
rev. 4.00, 03/04, page 390 of 462 table 17.15 dc characteristics (2) v cc = 2.7 v to 5.5 v, av cc = 2.7 v to 5.5 v, v ss =av ss = 0.0 v, unless otherwise specified values item symbol applicable pins test condition min typ max unit notes input low voltage v il res , wkp0 to wkp7 , irq0 , irq1, irqaec, p95 * 5 , v cc = 4.0 v to 5.5 v ? 0.3 ? v cc 0.2 v aevl, aevh, sck32 other than above ? 0.3 ? v cc 0.1 rxd32 v cc = 4.0 v to 5.5 v ? 0.3 ? v cc 0.3 v other than above ? 0.3 ? v cc 0.2 osc1 v cc = 4.0 v to 5.5 v ? 0.3 ? v cc 0.2 v other than above ? 0.3 ? v cc 0.1 p31 to p37, p40 to p43, p50 to p57, v cc = 4.0 v to 5.5 v ? 0.3 ? v cc 0.3 v p60 to p67, p70 to p77, p80, pa0 to pa3, pb0 to pb3 other than above ? 0.3 ? v cc 0.2 v oh v cc = 4.0 v to 5.5 v ?i oh =1.0ma v cc ?1.0 ? ? v output high voltage v cc = 4.0 v to 5.5 v ?i oh =0.5ma v cc ?0.5 ? ? p31 to p37, p40 to p42, p50 to p57, p60 to p67, p70 to p77, p80, pa0 to pa3 ?i oh =0.1ma v cc ?0.3 ? ?
rev. 4.00, 03/04, page 391 of 462 table 17.15 dc characteristics (3) v cc = 2.7 v to 5.5 v, av cc = 2.7 v to 5.5 v, v ss =av ss = 0.0 v, unless otherwise specified values item symbol applicable pins test condition min typ max unit notes output low voltage v ol v cc = 4.0 v to 5.5 v i ol =1.6ma ??0.6v p40 to p42 p50 to p57, p60 to p67, p70 to p77, p80, pa0 to pa3 i ol =0.4ma ? ? 0.5 p31 to p37 v cc = 4.0 v to 5.5 v i ol =10ma ??1.0 v cc = 4.0 v to 5.5 v i ol =1.6ma ??0.6 i ol =0.4ma ? ? 0.5 p90 to p93, p95 v cc = 4.0 v to 5.5 v i ol =25ma ??1.5 v cc = 4.0 v to 5.5 v i ol =15ma ??1.0 v cc = 4.0 v to 5.5 v i ol =10ma ??0.8 i ol =5ma ? ? 1.0 i ol =1.6ma ? ? 0.6 i ol =0.4ma ? ? 0.5 |i il | res ,p43 osc1, x1, p31 to p37, p40 to p42, p50 to p57, p60 to p67, p70 to p77, p80, irqaec, pa0 to pa3, p90 to p93, p95 v in =0.5vtov cc ? 0.5 v ??1.0a input/ output leakage current pb0 to pb3 v in =0.5vtoav cc ?0.5v ??1.0 ?i p v cc =5.0v, v in =0.0v 20 ? 200 a pull-up mos current p31 to p37, p50 to p57, p60 to p67 v cc =2.7v, v in =0.0v ?40? refer- ence value
rev. 4.00, 03/04, page 392 of 462 table 17.15 dc characteristics (4) v cc = 2.7 v to 5.5 v, av cc = 2.7 v to 5.5 v, v ss =av ss = 0.0 v, unless otherwise specified values item symbol applicable pins test condition min typ max unit notes input capaci- tance c in all input pins except power supply pin f=1mhz, v in =0.0v, t a =25 c ? ? 15.0 a active mode current consump- tion i ope1 v cc active (high-speed) mode v cc =2.7v, f osc =2mhz ?tbd?ma * 1 * 3 * 4 approx. max. value =1.1 typ. ?1.0? * 2 * 3 * 4 approx. max. value =1.1 typ. active (high-speed) mode v cc =5v, f osc =2mhz ?tbd? * 1 * 3 * 4 approx. max. value =1.1 typ. ?1.8? * 2 * 3 * 4 approx. max. value =1.1 typ. active (high-speed) mode v cc =5v, f osc =4mhz ?tbd? * 1 * 3 * 4 approx. max. value =1.1 typ. ?2.0? * 2 * 3 * 4 approx. max. value =1.1 typ. ?tbdtbd * 1 * 3 * 4 active (high-speed) mode v cc =5v, f osc =10mhz ?4.07.0 * 2 * 3 * 4
rev. 4.00, 03/04, page 393 of 462 table 17.15 dc characteristics (5) v cc = 2.7 v to 5.5 v, av cc = 2.7 v to 5.5 v, v ss =av ss = 0.0 v, unless otherwise specified values item symbol applicable pins test condition min typ max unit notes active mode current consump- tion i ope2 v cc active (medium- speed) mode v cc =2.7v, f osc =2mhz, osc /128 ?tbd?ma * 1 * 3 * 4 approx. max. value =1.1 typ. ?0.5? * 2 * 3 * 4 approx. max. value =1.1 typ. active (medium- speed) mode v cc =5v, f osc =2mhz, osc /128 ?tbd? * 1 * 3 * 4 approx. max. value =1.1 typ. ?0.8? * 2 * 3 * 4 approx. max. value =1.1 typ. active (medium- speed) mode v cc =5v, f osc =4mhz, osc /128 ?tbd? * 1 * 3 * 4 approx. max. value =1.1 typ. ?0.9? * 2 * 3 * 4 approx. max. value =1.1 typ. ?tbdtbd * 1 * 3 * 4 active (medium- speed) mode v cc =5v, f osc =10mhz, osc /128 ?1.23.0 * 2 * 3 * 4
rev. 4.00, 03/04, page 394 of 462 values item symbol applicable pins test condition min typ max unit notes sleep mode current consump- tion i sleep v cc v cc =2.7v, f osc =2mhz ?tbd?ma * 1 * 3 * 4 approx. max. value =1.1 typ. ?0.8? * 2 * 3 * 4 approx. max. value =1.1 typ. v cc =5v, f osc =2mhz ?tbd? * 1 * 3 * 4 approx. max. value =1.1 typ. ?0.9? * 2 * 3 * 4 approx. max. value =1.1 typ. v cc =5v, f osc =4mhz ?tbd? * 1 * 3 * 4 approx. max. value =1.1 typ. ?1.3? * 2 * 3 * 4 approx. max. value =1.1 typ. ?tbdtbd * 1 * 3 * 4 v cc =5v, f osc =10mhz ?2.25.0 * 2 * 3 * 4
rev. 4.00, 03/04, page 395 of 462 values item symbol applicable pins test condition min typ max unit notes i sub v cc ?tbd?a * 1 * 3 * 4 reference value subactive mode current consump- tion v cc =2.7v, lcd on, 32-khz crystal resonator used ( sub = w /8) ?10? * 2 * 3 * 4 reference value ?tbdtbd * 1 * 3 * 4 v cc =2.7v, lcd on, 32-khz crystal resonator used ( sub = w /2) ?3050 * 2 * 3 * 4 subsleep mode current consump- tion i subsp v cc v cc =2.7v, lcd on, 32-khz crystal resonator used ( sub = w /2) ?4.016a * 3 * 4 i watch v cc ?tbd? * 1 * 3 * 4 reference value v cc =2.7v, ta = 25 c, 32-khz crystal resonator used, lcd not used ?1.8? * 2 * 3 * 4 reference value watch mode current consump- tion v cc =2.7v, 32-khz crystal resonator used, lcd not used ?1.86.0 * 3 * 4 i stby v cc v cc =2.7v, ta = 25 c, 32-khz crystal resonator not used ?tbd?a * 1 * 3 * 4 reference value standby mode current consump- tion v cc =3.0v, ta = 25 c, 32-khz crystal resonator not used ?0.5? * 3 * 4 reference value 32-khz crystal resonator not used ?1.05.0 * 3 * 4 ram data retaining voltage v ram v cc 2.0 ? ? v
rev. 4.00, 03/04, page 396 of 462 values item symbol applicable pins test condition min typ max unit notes allowable output low current (per pin) i ol output pins except ports 3 and 9 v cc =4.0vto 5.5 v ??2.0ma port 3 v cc =4.0vto 5.5 v ? ? 10.0 output pins except port 9 ??0.5 ? ? 15.0 * 5 p90 to p93, p95 v cc =4.0vto 5.5 v ? ? 10.0 ??8.0 allowable output low current (total) i ol output pins except ports 3 and 9 v cc =4.0vto 5.5 v ? ? 40.0 ma port 3 v cc =4.0vto 5.5 v ? ? 80.0 output pins except port 9 ? ? 20.0 port 9 ? ? 80.0 ?i oh all output pins v cc =4.0vto 5.5 v ??2.0ma allowable output high current (per pin) other than above ??0.2 ?i oh all output pins v cc =4.0vto 5.5 v ? ? 15.0 ma allowable output high current (total) other than above ? ? 10.0 notes: connect the test pin to v ss . 1. applies to the mask-rom version. 2. applies to the f-ztat version.
rev. 4.00, 03/04, page 397 of 462 3. pin states when current consumption is measured. mode res res res res pin internal state other pins lcd power supply oscillator pins active (high-speed) mode (i ope1 ) active (medium- speed) mode (i ope2 ) v cc only cpu operates v cc stops sleep mode v cc only all on-chip timers operate v cc stops system clock: crystal resonator subclock: pin x 1 =gnd subactive mode v cc only cpu operates v cc stops subsleep mode v cc only all on-chip timers operate cpu stops v cc stops watch mode v cc only clock time base operates cpu stops v cc stops system clock: crystal resonator subclock: crystal resonator standby mode v cc cpu and timers both stop v cc stops system clock: crystal resonator subclock: pin x 1 =gnd 4. except current which flows to the pull-up mos or output buffer 5. used when user mode or boot mode is determined after canceling a reset in the f- ztat version
rev. 4.00, 03/04, page 398 of 462 17.6.3 ac characteristics table 17.16 lists the control signal timing and table 17.17 lists the serial interface timing. table 17.16 control signal timing v cc = 2.7 v to 5.5 v, av cc = 2.7 v to 5.5 v, v ss =av ss = 0.0 v, unless otherwise specified values item symbol applicable pins test condition min typ max unit reference figure f osc osc 1 ,osc 2 2.0 ? 16.0 mhz system clock oscillation frequency on-chip oscillator selected 0.8 ? 2.0 t osc osc 1 ,osc 2 62.5 ? 500 ns figure 17.1 osc clock ( osc ) cycle time on-chip oscillator selected 500 ? 1250 t cyc 2 ? 128 t osc system clock ( ) cycle time ? ? 160 s subclock oscillation frequency f w x 1 ,x 2 ? 32.768 ? khz watch clock ( w ) cycle time t w x 1 ,x 2 ? 30.5 ? s figure 17.1 subclock ( sub ) cycle time t subcyc 2? 8 t w * instruction cycle time 2? ? t cyc t subcyc oscillation stabilization time t rc osc 1 , osc 2 ?? 20 ms x 1 ,x 2 ?? 2.0 s external clock high width t cph osc 1 25 ? ? ns figure 17.1 external clock low width t cpl osc 1 25 ? ? ns figure 17.1 external clock rise time t cpr osc 1 ? ? 6 ns figure 17.1 external clock fall time t cpf osc 1 ? ? 6 ns figure 17.1 res pin low width t rel res 10 ? ? t cyc figure 17.2
rev. 4.00, 03/04, page 399 of 462 values item symbol applicable pins test condition min typ max unit reference figure input pin high width t ih irq0 , irq1 , irqaec, wkp0 to wkp7 , 2? ? t cyc t subcyc figure 17.3 aevl, aevh 0.5 ? ? t osc input pin low width t il irq0 , irq1 , irqaec, wkp0 to wkp7 , 2? ? t cyc t subcyc figure 173 aevl, aevh 0.5 ? ? t osc note: * determined by the sa1 and sa0 bits in the system control register 2 (syscr2). table 17.17 serial interface (sci3) timing v cc = 2.7 v to 5.5 v, av cc = 2.7 v to 5.5 v, v ss =av ss = 0.0 v, unless otherwise specified values item symbol test condition min typ max unit reference figure asynchronous t scyc 4 ? ? figure 17.4 input clock cycle clocked synchronous 6 ? ? t cyc or t subcyc input clock pulse width t sckw 0.4 ? 0.6 t scyc figure 17.4 transmit data delay time (clocked synchronous) t txd ??1t cyc or t subcyc figure 17.5 receive data setup time (clocked synchronous) t rxs 400.0 ? ? ns figure 17.5 receive data hold time (clocked synchronous) t rxh 400.0 ? ? ns figure 17.5
rev. 4.00, 03/04, page 400 of 462 17.6.4 a/d converter characteristics table 17.18 shows the a/d converter characteristics. table 17.18 a/d converter characteristics v cc = 2.7 v to 5.5 v, av cc = 2.7 v to 5.5 v, v ss =av ss = 0.0 v, unless otherwise specified values item symbol applicable pins test condition min typ max unit reference figure analog power supply voltage av cc av cc 2.7 ? 5.5 v * 1 analog input voltage av in an 0 to an 3 ?0.3 ? av cc +0.3 v ai ope av cc av cc = 5.0 v ? ? 1.5 ma analog power supply current ai stop1 av cc ? 600 ? a * 2 reference value ai stop2 av cc ??5.0 a * 3 analog input capacitance c ain an 0 to an 3 ? ? 15.0 pf allowable signal source impedance r ain ? ? 10.0 k ? resolution (data length) ? ? 10 bit nonlinearity error av c c =4.0v to 5.5 v ??3.5 lsb av c c =2.7v to 5.5 v ??7.5 quantization error ? ? 0.5 lsb absolute accuracy av c c =4.0v to 5.5 v ? 2.0 4.0 lsb av c c =2.7v to 5.5 v ? 2.0 8.0 conversion time 7.8 ? 124 s notes: 1. set av cc =v cc when the a/d converter is not used. 2. ai stop1 is the current in active and sleep modes while the a/d converter is idle. 3. ai stop2 is the current at reset and in standby, watch, subactive, and subsleep modes while the a/d converter is idle.
rev. 4.00, 03/04, page 401 of 462 17.6.5 lcd characteristics table 17.19 shows the lcd characteristics. table 17.19 lcd characteristics v cc = 2.7 v to 5.5 v, av cc = 2.7 v to 5.5 v, v ss =av ss = 0.0 v, unless otherwise specified values item symbol applicable pins test condition min typ max unit reference figure segment driver step-down voltage v ds seg 1 to seg 25 i d =2a v1 = 2.7 v to 5.5 v ??0.6v * 1 common driver step-down voltage v dc com 1 to com 4 i d =2a v1 = 2.7 v to 5.5 v ??0.3v * 1 lcd power supply split-resistance r lcd between v1 and v ss 1.5 3.0 7.0 m ? liquid crystal display voltage v lcd v 1 2.2 ? 5.5 v * 2 notes: 1. the voltage step-down from power supply pins v1, v2, v3, and v ss to each segment pinorcommonpin. 2. when the liquid crystal display voltage is supplied from an external power supply, ensure that the following relationship is maintained: v cc v1 v2 v3 v ss .
rev. 4.00, 03/04, page 402 of 462 17.6.6 flash memory characteristics table 17.20 flash memory characteristics condition a: av cc = 2.7 v to 5.5 v, v ss =av ss =0.0v,v cc =2.7vto5.5v(rangeof operating voltage when reading), v cc = 3.0 v to 5.5 v (range of operating voltage when programming/erasing), t a = ?20c to +75c (range of operating temperature when programming/erasing: product with regular specifications, product with wide- range temperature specifications) values item symbol test conditions min typ max unit programming time * 1 * 2 * 4 t p ? 7 200 ms/128 bytes erase time * 1 * 3 * 5 t e ? 100 1200 ms/block reprogramming count n wec 1000 * 8 10000 * 9 ?times data retain period t drp 10 * 10 ??year programming wait time after swe-bit setting * 1 x 1 ??s wait time after psu-bit setting * 1 y 50??s z1 1 n 6 283032s z2 7 n 1000 198 200 202 s wait time after p-bit setting * 1 * 4 z3 additional programming 8 1012s wait time after p-bit clear * 1 5 ??s wait time after psu-bit clear * 1 5 ??s wait time after pv-bit setting * 1 4 ??s wait time after dummy write * 1 2 ??s wait time after pv-bit clear * 1 2 ??s wait time after swe-bit clear * 1 100 ? ? s maximum programming count * 1 * 4 * 5 n ? ? 1000 times
rev. 4.00, 03/04, page 403 of 462 values item symbol test conditions min typ max unit wait time after swe-bit setting * 1 x 1 ??s wait time after esu-bit setting * 1 y 100 ? ? s wait time after e-bit setting * 1 * 6 z 10 ? 100 ms wait time after e-bit clear * 1 10??s wait time after esu-bit clear * 1 10??s wait time after ev-bit setting * 1 20??s wait time after dummy write * 1 2 ??s wait time after ev-bit clear * 1 4 ??s wait time after swe-bit clear * 1 100 ? ? s erase maximum erase count * 1 * 6 * 7 n ? ? 120 times notes: 1. set the times according to the program/erase algorithms. 2. programming time per 128 bytes (shows the total period for which the p bit in flmcr1 is set. it does not include the programming verification time.) 3. block erase time (shows the total period for which the e bit in flmcr1 is set. it does not include the erase verification time.) 4. maximum programming time (t p (max)) t p (max) = wait time after p-bit setting (z) maximum number of writes (n) 5. the maximum number of writes (n) should be set according to the actual set value of z1, z2, and z3 to allow programming within the maximum programming time (t p (max)). the wait time after p-bit setting (z1 and z2) should be alternated according to the number of writes (n) as follows: 1 n 6z1=30s 7 n 1000 z2 = 200 s 6. maximum erase time (t e (max)) t e (max) = wait time after e-bit setting (z) maximum erase count (n) 7. the maximum number of erases (n) should be set according to the actual set value of z to allow erasing within the maximum erase time (t e (max)). 8. this minimum value guarantees all characteristics after reprogramming (the guaranteed range is from 1 to the minimum value). 9. reference value when the temperature is 25 c (normally reprogramming will be performed by this count). 10. this is a data retain characteristic when reprogramming is performed within the specification range including this minimum value.
rev. 4.00, 03/04, page 404 of 462 17.6.7 power supply voltage detection circuit characteristics (preliminary) table 17.21 power supply voltage detection circuit characteristics (1) v cc = 2.7 v to 5.5 v, av cc = 2.7 v to 5.5 v, v ss =av ss = 0.0 v, unless otherwise specified rated values item symbol test conditions min typ max unit lvdr operation drop voltage * v lvdrmin 1.0??v lvd stabilization time v lvdon 100 ? ? s standby mode current consumption i stby lvde = 1 v cc =5.0v 32 oscillator not used ? ? 100 a note: * in some cases no reset may occur if the power supply voltage, v cc ,dropsbelow vlvdrmin = 1.0 v and then rises, so thorough evaluation is called for. table 17.22 power supply voltage detection circuit characteristics (2) using on-chip reference voltage and ladder resistor (vrefsel = vintdsel = vintusel = 0) rated values item symbol test conditions min typ max unit power supply drop detection voltage vint(d) * 3 lvdsel = 0 3.3 3.7 4.2 v power supply rise detection voltage vint(u) * 3 lvdsel = 0 3.6 4.0 4.5 v reset detection voltage 1 * 1 vreset1 * 3 lvdsel = 0 2.0 2.3 2.7 v reset detection voltage 2 * 2 vreset2 * 3 lvdsel = 1 2.7 3.3 3.9 v notes: 1. the above function should be used in conjunction with the voltage drop/rise detection function. 2. low-voltage detection reset should be selected for low-voltage detection reset only. 3. the values of vint(d), vint(u), vreset1, and vreset2 change relative to each other. example: if vint(d) is the minimum value, vint(u), vreset1, and vreset2 are also the minimum values.
rev. 4.00, 03/04, page 405 of 462 table 17.23 power supply voltage detection circuit characteristics (3) using on-chip reference voltage and detect voltage external input (vrefsel = 0, vintdsel and vintusel = 1) rated values item symbol test condition min typ max unit extd/extu interrupt detection level vexd 0.80 1.20 1.60 v v cc = 2.7 to 3.3 v ?0.3 ? v cc +0.3orav cc + 0.3, whichever is lower v extd/extu pin input voltage * 2 vextd * 1 vextu * 1 v cc = 3.3 to 5.5 v ?0.3 ? 3.6 or av cc +0.3, whichever is lower v notes: 1. the vextd voltage must always be greater than the vextu voltage. 2. the maximum input voltage of the extd and extu pins is 3.6 v.
rev. 4.00, 03/04, page 406 of 462 table 17.24 power supply voltage detection circuit characteristics (4) using external reference voltage and ladder resistor (vrefsel = 1, vintdsel = vintusel = 0) rated values item symbol test condition min typ max unit power supply drop detection voltage vint(d) * 1 lvdsel = 0 3.08 * (vref1 ? 0.1) 3.08 * vref1 3.08 * (vref1 + 0.1) v vref input voltage (vint(d)) vref1 * 2 vint(d) 0.98 ? 1.68 v power supply rise detection voltage vint(u) * 1 lvdsel = 0 3.33 * (vref2 ? 0.1) 3.33 * vref2 3.33 * (vref2 + 0.1) v vref input voltage (vint(u)) vref2 * 2 vint(u) 0.91 ? 1.55 v reset detection voltage 1 vreset1 * 1 lvdsel = 0 1.91 * (vref3 ? 0.1) 1.91 * vref3 1.91 * (vref3 + 0.1) v vref input voltage (vreset1) vref3 * 2 vreset1 0.89 ? 2.77 v reset detection voltage 2 vreset2 * 1 lvdsel = 1 2.76 * (vref4 ? 0.1) 2.76 * vref4 2.76 * (vref4 + 0.1) v vref input voltage (vreset2) vref4 * 2 vreset2 1.08 ? 1.89 v notes: 1. the values of vint(d), vint(u), vreset1, and vreset2 change relative to each other. example: if vint(d) is the minimum value, vint(u), vreset1, and vreset2 are also the minimum values. 2. the vref input voltage is calculated using the following formula. 2.7 v (= v cc min) < vint(d), vint(u), vreset2 < 5.5 v (= v cc max) 1.5 v (= ram retention voltage) < vreset1 < 5.5 v (= v cc max) vref1: 2.7 < 3.08 * (vref1 ? 0.1), 3.08 * (vref1 + 0.1) < 5.5 0.98 < vref1 < 1.68 vref2: 2.7 < 3.33 * (vref2 ? 0.1), 3.33 * (vref2 + 0.1) < 5.5 0.91 < vref2 < 1.55 vref3: 1.5 < 1.91 * (vref3 ? 0.1), 1.91 * (vref3 + 0.1) < 5.5 0.89 < vref3 < 2.77 vref4: 2.7 < 2.76 * (vref4 ? 0.1), 2.76 * (vref4 + 0.1) < 5.5 1.08 < vref4 < 1.89
rev. 4.00, 03/04, page 407 of 462 table 17.25 power supply voltage detection circuit characteristics (5) using external reference voltage and detect voltage external input (vrefsel = vintdsel = vintusel = 1) rated values item symbol test condition min typ max unit comparator detection accuracy vcdl | vextu ? vref | |vextd?vref| 0.1 ? ? v v cc = 2.7 to 3.3 v ?0.3 ? v cc +0.3or av cc +0.3, whichever is lower v extd/extu pin input voltage vextd * vextu * v cc = 3.3 to 5.5 v ?0.3 ? 3.6 or av cc + 0.3, whichever is lower v vref pin input voltage vref5 v cc = 2.7 to 5.5 v 0.8 ? 2.8 v note: * the vextd voltage must always be greater than the vextu voltage. 17.6.8 power-on reset circuit characteristics (preliminary) table 17.26 power-on reset circuit characteristics v cc = 2.7 v to 5.5 v, av cc = 2.7 v to 5.5 v, v ss =av ss = 0.0 v, unless otherwise specified rated values item symbol test condition min typ max unit res pin pull-up resistance r res 65 100 ? k ? power-on reset start voltage v por ? ? 100 mv note: make sure to drop the power supply voltage, v cc , to below vpor = 100 mv and then raise it after the res pin load had thoroughly dissipated. to drain the load of the res pin, attaching a diode to the v cc side is recommended. the power-on reset function may not work properly if the power supply voltage, v cc , is raised from a level exceeding 100 mv.
rev. 4.00, 03/04, page 408 of 462 17.6.9 watchdog timer characteristics table 17.27 watchdog timer characteristics av cc = 2.7 v to 5.5 v, v ss =av ss = 0.0 v, unless otherwise specified rated values item symbol applicable pins test condition min typ max unit note on-chip oscillator overflow time t ovf 0.2 0.4 ? s * note: * when the on-chip oscillator is selected, the timer counts from 0 to 255, indicating the time remaining until an internal reset is generated. 17.7 operation timing figures 17.1 to 17.5 show the operation timings. osc1 , x 1 t osc, t w v ih v il t cpr t cph t cpl t cpf figure 17.1 clock input timing t rel v il figure 17.2 res res res res low width timing t il v ih v il t ih , , to , irqaec, aevl, aevh figure 17.3 input timing
rev. 4.00, 03/04, page 409 of 462 sck32 t sckw t scyc figure 17.4 sck3 input clock timing sck 32 txd32 (transmit data) rxd32 (receive data) t scyc v ih or v oh * v il or v ol * t txd t rxs t rxh v oh * v ol * note: * output timing reference levels load conditions are shown in figure 17.6. output high output low v oh = 1/2v cc + 0.2 v v ol = 0.8 v figure 17.5 sci3 input/output timing in clocked synchronous mode 17.8 output load condition v cc 2.4 k ? ? figure 17.6 output load circuit
rev. 4.00, 03/04, page 410 of 462 17.9 resonator equivalent circuit osc 1 l s c s c o r s osc 2 crystal resonator parameter frequency (mhz) r s (max) c o (max) 4.193 100 ? ? ? ? ? ? figure 17.7 resonator equivalent circuit osc 1 crystal resonator parameter (nominal values by manufacturer) ceramic resonator parameter (1) (nominal values by manufacturer) ceramic resonator parameter (2) (nominal values by manufacturer) 4 frequency osc 2 l s c s c o r s 100 ? ? ? figure 17.8 resonator equivalent circuit
rev. 4.00, 03/04, page 411 of 462 17.10 usage note the ztat, f-ztat, and mask rom versions satisfy the electrical characteristics shown in this manual, but actual electrical characteristic values, operating margins, noise margins, and other properties may vary due to differences in manufacturing process, on-chip rom, layout patterns, andsoon. when system evaluation testing is carried out using the ztat or f-ztat version, the same evaluation testing should also be conducted for the mask rom version when changing over to that version.
rev. 4.00, 03/04, page 412 of 462
rev. 4.00, 03/04, page 413 of 462 appendix a instruction set a.1 instruction list operation notation symbol description rd8/16 general register (destination) (8 or 16 bits) rs8/16 general register (source) (8 or 16 bits) rn8/16 general register (8 or 16 bits ) ccr condition-code register n n (negative) flag in ccr z z (zero) flag in ccr v v (overflow) flag in ccr c c (carry) flag in ccr pc program counter sp stack pointer #xx:3/8/16 immediate data (3, 8, or 16 bits) d:8/16 displacement (8 or 16 bits) @aa:8/16 absolute address (8 or 16 bits) + addition ? subtraction multiplication division logical and logical or logical exclusive or move ? logical complement
rev. 4.00, 03/04, page 414 of 462 condition code notation symbol description changed according to execution result * undetermined (no guaranteed value) 0 cleared to 0 ? not affected by execution result
rev. 4.00, 03/04, page 415 of 462 table a.1 instruction set mnemonic operand size operation mov.b #xx:8, rd mov.b rs, rd mov.b @rs, rd mov.b @(d:16, rs), rd mov.b @rs+, rd mov.b @aa:8, rd mov.b @aa:16, rd mov.b rs, @rd mov.b rs, @(d:16, rd) mov.b rs, @-rd mov.b rs, @aa:8 mov.b rs, @aa:16 mov.w #xx:16, rd mov.w rs, rd mov.w @rs, rd mov.w @(d:16, rs), rd mov.w @rs+, rd mov.w @aa:16, rd mov.w rs, @rd mov.w rs, @(d:16, rd) b b b b b b b b b b b b w w w w w w w w 2 4 2 2 2 2 2 2 4 4 4 4 2 2 2 #xx:8 rd8 rs8 rd8 @rs16 rd8 @(d:16, rs16) rd8 @rs16 rd8 rs16+1 rs16 @aa:8 rd8 @aa:16 rd8 rs8 @rd16 rs8 @(d:16, rd16) rd16-1 rd16 rs8 @rd16 rs8 @aa:8 rs8 @aa:16 #xx:16 rd rs16 rd16 @rs16 rd16 @(d:16, rs16) rd16 @rs16 rd16 rs16+2 rs16 @aa:16 rd16 rs16 @rd16 rs16 @(d:16, rd16) 2 4 2 4 4 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 2 2 4 6 6 4 6 4 6 6 4 6 4 2 4 6 6 6 4 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mov addressing modes/instruction length (bytes) condition code number of execution states #xx:8/16 rn @rn @(d:16, rn) @-rn/@rn+ @aa:8/16 @(d:8, pc) @@aa ? i h n z v c
rev. 4.00, 03/04, page 416 of 462 mov.w rs, @-rd mov.w rs, @aa:16 pop rd push rs add.b #xx:8, rd add.b rs, rd add.w rs, rd addx.b #xx:8, rd addx.b rs, rd adds.w #1, rd adds.w #2, rd inc.b rd daa.b rd sub.b rs, rd sub.w rs, rd subx.b #xx:8, rd subx.b rs, rd w w w w b b w b b w w b b b w b b 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 rd16-2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? (2) (2) ? ? (2) (2) ? ? ? ? (1) ? ? ? * (1) ? ? ? ? ? ? ? ? ? (3) 6 6 6 6 2 2 2 2 2 2 2 2 2 2 2 2 2 0 0 0 0 ? ? * mov pop push add addx adds inc daa sub subx #xx:8/16 rn @rn @(d:16, rn) @-rn/@rn+ @aa:8/16 @(d:8, pc) @@aa ? ihnzvc mnemonic operand size operation addressing modes/instruction length (bytes) condition code number of execution states
rev. 4.00, 03/04, page 417 of 462 subs.w #1, rd subs.w #2, rd dec.b rd das.b rd neg.b rd cmp.b #xx:8, rd cmp.b rs, rd cmp.w rs, rd mulxu.b rs, rd divxu.b rs, rd and.b #xx:8, rd and.b rs, rd or.b #xx:8, rd or.b rs, rd xor.b #xx:8, rd xor.b rs, rd not.b rd shal.b rd w w b b b b b w b b b b b b b b b b 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 rd16-1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? * (1) ? ? ? ? ? ? ? ? ? ? ? ? ? (5) ? ? ? (6) ? ? ? ? ? ? ? ? ? ? ? ? ? 2 2 2 2 2 2 2 2 14 14 2 2 2 2 2 2 2 2 ? ? * ? ? 0 0 0 0 0 0 0 subs dec das neg cmp mulxu divxu and or xor not shal #xx:8/16 rn @rn @(d:16, rn) @-rn/@rn+ @aa:8/16 @(d:8, pc) @@aa ? ihnzvc c b 7 b 0 0 mnemonic operand size operation addressing modes/instruction length (bytes) condition code number of execution states
rev. 4.00, 03/04, page 418 of 462 shar.b rd shll.b rd shlr.b rd rotxl.b rd rotxr.b rd rotl.b rd rotr.b rd bset #xx:3, rd bset #xx:3, @rd b b b b b b b b b 2 2 2 2 2 2 2 2 4 (#xx:3 of rd8) 1 (#xx:3 of @rd16) 1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 ? ? ? ? ? ? 2 2 2 2 2 2 2 2 8 0 0 0 0 0 0 0 ? ? shar shll shlr rotxl rotxr rotl rotr bset ? ? #xx:8/16 rn @rn @(d:16, rn) @-rn/@rn+ @aa:8/16 @(d:8, pc) @@aa ? ihnzvc c b 7 b 0 c b 7 b 0 c 0 0 c b 7 b 0 c b 7 b 0 c b 7 b 0 b 7 b 0 c b 7 b 0 mnemonic operand size operation addressing modes/instruction length (bytes) condition code number of execution states
rev. 4.00, 03/04, page 419 of 462 bset #xx:3, @aa:8 bset rn, rd bset rn, @rd bset rn, @aa:8 bclr #xx:3, rd bclr #xx:3, @rd bclr #xx:3, @aa:8 bclr rn, rd bclr rn, @rd bclr rn, @aa:8 bnot #xx:3, rd bnot #xx:3, @rd bnot #xx:3, @aa:8 bnot rn, rd bnot rn, @rd bnot rn, @aa:8 btst #xx:3, rd btst #xx:3, @rd btst #xx:3, @aa:8 btst rn, rd b b b b b b b b b b b b b b b b b b b b 2 2 2 2 2 2 2 4 4 4 4 4 4 (#xx:3 of @aa:8) 1 (rn8 of rd8) 1 (rn8 of @rd16) 1 (rn8 of @aa:8) 1 (#xx:3 of rd8) 0 (#xx:3 of @rd16) 0 (#xx:3 of @aa:8) 0 (rn8 of rd8) 0 (rn8 of @rd16) 0 (rn8 of @aa:8) 0 (#xx:3 of rd8) (#xx:3 of rd8) (#xx:3 of @rd16) (#xx:3 of @rd16) (#xx:3 of @aa:8) (#xx:3 of @aa:8) (rn8 of rd8) (rn8 of rd8) (rn8 of @rd16) (rn8 of @rd16) (rn8 of @aa:8) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 8 2 8 8 2 8 8 2 8 8 2 8 8 2 8 8 2 6 6 2 bset bclr bnot btst #xx:8/16 rn @rn @(d:16, rn) @-rn/@rn+ @aa:8/16 @(d:8, pc) @@aa ? ihnzvc mnemonic operand size operation addressing modes/instruction length (bytes) condition code number of execution states
rev. 4.00, 03/04, page 420 of 462 btst rn, @rd btst rn, @aa:8 bld #xx:3, rd bld #xx:3, @rd bld #xx:3, @aa:8 bild #xx:3, rd bild #xx:3, @rd bild #xx:3, @aa:8 bst #xx:3, rd bst #xx:3, @rd bst #xx:3, @aa:8 bist #xx:3, rd bist #xx:3, @rd bist #xx:3, @aa:8 band #xx:3, rd band #xx:3, @rd band #xx:3, @aa:8 biand #xx:3, rd biand #xx:3, @rd biand #xx:3, @aa:8 bor #xx:3, rd bor #xx:3, @rd bor #xx:3, @aa:8 b b b b b b b b b b b b b b b b b b b b b b b 2 2 2 2 2 2 2 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 (rn8 of @rd16) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 6 6 2 6 6 2 6 6 2 8 8 2 8 8 2 6 6 2 6 6 2 6 6 btst bld bild bst bist band biand bor #xx:8/16 rn @rn @(d:16, rn) @-rn/@rn+ @aa:8/16 @(d:8, pc) @@aa ? ihnzvc mnemonic operand size operation addressing modes/instruction length (bytes) condition code number of execution states
rev. 4.00, 03/04, page 421 of 462 bior #xx:3, rd bior #xx:3, @rd bior #xx:3, @aa:8 bxor #xx:3, rd bxor #xx:3, @rd bxor #xx:3, @aa:8 bixor #xx:3, rd bixor #xx:3, @rd bixor #xx:3, @aa:8 bra d:8 (bt d:8) brn d:8 (bf d:8) bhi d:8 bls d:8 bcc d:8 (bhs d:8) bcs d:8 (blo d:8) bne d:8 beq d:8 bvc d:8 bvs d:8 bpl d:8 bmi d:8 bge d:8 blt d:8 bgt d:8 ble d:8 b b b b b b b b b ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 2 2 2 4 4 4 c ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 2 6 6 2 6 6 2 6 6 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 bior bxor bixor b cc #xx:8/16 rn @rn @(d:16, rn) @-rn/@rn+ @aa:8/16 @(d:8, pc) @@aa ? ihnzvc mnemonic operand size operation branching condition addressing modes/instruction length (bytes) condition code number of execution states
rev. 4.00, 03/04, page 422 of 462 jmp @rn jmp @aa:16 jmp @@aa:8 bsr d:8 jsr @rn jsr @aa:16 jsr @@aa:8 rts rte ? ? ? ? ? ? ? ? ? 2 2 pc rn16 pc aa:16 pc @aa:8 sp-2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 4 6 8 6 6 8 8 8 10 jmp bsr jsr rts rte #xx:8/16 rn @rn @(d:16, rn) @-rn/@rn+ @aa:8/16 @(d:8, pc) @@aa ? ihnzvc mnemonic operand size operation addressing modes/instruction length (bytes) condition code number of execution states
rev. 4.00, 03/04, page 423 of 462 sleep ldc #xx:8, ccr ldc rs, ccr stc ccr, rd andc #xx:8, ccr orc #xx:8, ccr xorc #xx:8, ccr nop eepmov ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
rev. 4.00, 03/04, page 424 of 462 a.2 operation code map table a.2 is an operation code map. it shows the operation codes contained in the first byte of the instruction code (bits 15 to 8 of the first instruction word). instruction when first bit of byte 2 (bit 7 of first instruction word) is 0. instruction when first bit of byte 2 (bit 7 of first instruction word) is 1.
rev. 4.00, 03/04, page 425 of 462 table a.2 operation code map 0 1 2 3 4 5 6 7 8 9 a b c d e f add addx cmp subx or xor and mov 0 nop bra mulxu 1 sleep brn divxu 2 stc bhi 3 ldc bls 4 orc or bcc rts 5 xorc xor bcs bsr 6 andc and bne rte 7 ldc beq 8 bvc add sub mov cmp bit manipulation instructions mov * 9 bvs mov a inc dec bpl jmp b adds subs bmi eepmov c bge d blt e addx subx bgt jsr f daa das ble bset bnot bclr btst mov shll shal shlr shar rotxl rotl rotxr rotr not neg bst bist blt bild band biand bxor bixor bor bior note: * the push and pop instructions are identical in machine language to mov instructions. low high
rev. 4.00, 03/04, page 426 of 462 a.3 number of execution states the status of execution for each instruction of the h8/300l cpu and the method of calculating the number of states required for instruction execution are shown below. table a.4 shows the number of cycles of each type occurring in each instruction, such as instruction fetch and data read/write. table a.3 shows the number of states required for each cycle. the total number of states required for execution of an instruction can be calculated by the following expression: execution states = i s i +j s j +k s k +l s l +m s m +n s n examples: when an instruction is fetched from the on-chip rom, and the on-chip ram is accessed. bset #0, @ff00 from table a.4: i=l=2, j=k=m=n=0 from table a.3: s i =2, s l =2 number of states required for execution = 2 2+2 2=8 when an instruction is fetched from the on-chip rom, a branch address is read from the on-chip rom, and the on-chip ram is used for stack area. jsr @@ 30 from table a.4: i = 2, j = k = 1, l = m = n = 0 from table a.3: s i =s j =s k =2 number of states required for execution = 2 2+1 2+ 1 2=8
rev. 4.00, 03/04, page 427 of 462 table a.3 number of states required for execution execution status access location (instruction cycle) on-chip memory on-chip peripheral module instruction fetch s i 2? branch address read s j stack operation s k byte data access s l 2or3 * word data access s m ? internal operation s n 1 note: * depends on which on-chip peripheral module is accessed. see section 16.1, register addresses (address order). table a.4 number of cycles in each instruction instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n add add.b #xx:8, rd add.b rs, rd add.w rs, rd 1 1 1 adds adds.w #1, rd adds.w #2, rd 1 1 addx addx.b #xx:8, rd addx.b rs, rd 1 1 and and.b #xx:8, rd and.b rs, rd 1 1 andc andc #xx:8, ccr 1 band band #xx:3, rd band #xx:3, @rd band #xx:3, @aa:8 1 2 2 1 1
rev. 4.00, 03/04, page 428 of 462 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n bcc bra d:8 (bt d:8) brn d:8 (bf d:8) bhi d:8 bls d:8 bcc d:8 (bhs d:8) bcs d:8 (blo d:8) bne d:8 beq d:8 bvc d:8 bvs d:8 bpl d:8 bmi d:8 bge d:8 2 2 2 2 2 2 2 2 2 2 2 2 2 bcc blt d:8 bgt d:8 ble d:8 2 2 2 bclr bclr #xx:3, rd bclr #xx:3, @rd bclr #xx:3, @aa:8 bclr rn, rd bclr rn, @rd bclr rn, @aa:8 1 2 2 1 2 2 2 2 2 2 biand biand #xx:3, rd biand #xx:3, @rd biand #xx:3, @aa:8 1 2 2 1 1 bild bild #xx:3, rd bild #xx:3, @rd bild #xx:3, @aa:8 1 2 2 1 1 bior bior #xx:3, rd bior #xx:3, @rd bior #xx:3, @aa:8 1 2 2 1 1 bist bist #xx:3, rd bist #xx:3, @rd bist #xx:3, @aa:8 1 2 2 2 2
rev. 4.00, 03/04, page 429 of 462 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n bixor bixor #xx:3, rd bixor #xx:3, @rd bixor #xx:3, @aa:8 1 2 2 1 1 bld bld #xx:3, rd bld #xx:3, @rd bld #xx:3, @aa:8 1 2 2 1 1 bnot bnot #xx:3, rd bnot #xx:3, @rd bnot #xx:3, @aa:8 bnot rn, rd bnot rn, @rd bnot rn, @aa:8 1 2 2 1 2 2 2 2 2 2 bor bor #xx:3, rd bor #xx:3, @rd bor #xx:3, @aa:8 1 2 2 1 1 bset bset #xx:3, rd bset #xx:3, @rd bset #xx:3, @aa:8 bset rn, rd bset rn, @rd bset rn, @aa:8 1 2 2 1 2 2 2 2 2 2 bsr bsr d:8 2 1 bst bst #xx:3, rd bst #xx:3, @rd bst #xx:3, @aa:8 1 2 2 2 2 btst btst #xx:3, rd btst #xx:3, @rd btst #xx:3, @aa:8 btst rn, rd btst rn, @rd btst rn, @aa:8 1 2 2 1 2 2 1 1 1 1 bxor bxor #xx:3, rd bxor #xx:3, @rd bxor #xx:3, @aa:8 1 2 2 1 1
rev. 4.00, 03/04, page 430 of 462 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n cmp cmp.b #xx:8, rd cmp.b rs, rd cmp.w rs, rd 1 1 1 daa daa.b rd 1 das das.b rd 1 dec dec.b rd 1 divxu divxu.b rs, rd 1 12 eepmov eepmov 2 2n+2 * 1 inc inc.b rd 1 jmp jmp @rn jmp @aa:16 jmp @@aa:8 2 2 21 2 2 jsr jsr @rn jsr @aa:16 jsr @@aa:8 2 2 21 1 1 1 2 ldc ldc #xx:8, ccr ldc rs, ccr 1 1 mov mov.b #xx:8, rd mov.b rs, rd mov.b @rs, rd mov.b @(d:16, rs), rd mov.b @rs+, rd mov.b @aa:8, rd mov.b @aa:16, rd mov.b rs, @rd mov.b rs, @(d:16, rd) mov.b rs, @-rd mov.b rs, @aa:8 mov.b rs, @aa:16 mov.w #xx:16, rd mov.w rs, rd mov.w @rs, rd mov.w @(d:16, rs), rd mov.w @rs+, rd 1 1 1 2 1 1 2 1 2 1 1 2 2 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2
rev. 4.00, 03/04, page 431 of 462 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n mov mov.w @aa:16, rd mov.w rs, @rd mov.w rs, @(d:16, rd) mov.w rs, @-rd mov.w rs, @aa:16 2 1 2 1 2 1 1 1 1 1 2 mulxu mulxu.b rs, rd 1 12 neg neg.b rd 1 nop nop 1 not not.b rd 1 or or.b #xx:8, rd or.b rs, rd 1 1 orc orc #xx:8, ccr 1 rotl rotl.b rd 1 rotr rotr.b rd 1 rotxl rotxl.b rd 1 rotxr rotxr.b rd 1 rte rte 2 2 2 rts rts 2 1 2 shal shal.b rd 1 shar shar.b rd 1 shll shll.b rd 1 shlr shlr.b rd 1 sleep sleep 1 stc stc ccr, rd 1 sub sub.b rs, rd sub.w rs, rd 1 1 subs subs.w #1, rd subs.w #2, rd 1 1 pop pop rd 1 1 2 push push rs 1 1 2 subx subx.b #xx:8, rd subx.b rs, rd 1 1
rev. 4.00, 03/04, page 432 of 462 instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n xor xor.b #xx:8, rd xor.b rs, rd 1 1 xorc xorc #xx:8, ccr 1 note: n: specified value in r4l. the source and destination operands are accessed n+1 times respectively.
rev. 4.00, 03/04, page 433 of 462 appendix b i/o port block diagrams b.1 port 3 block diagrams p3 n v cc v cc pucr3 internal data bus pmr3 pdr3 pcr3 aec module v ss aevh(p3 6 ) aevl(p3 7 ) pdr3: pcr3: pmr3: pucr3: port data register 3 port control register 3 port mode register 3 port pull-up control register 3 n = 7 or 6 figure b.1(a) port 3 block diagram (pins p37 and p36)
rev. 4.00, 03/04, page 434 of 462 p35 v cc v cc pucr3 internal data bus pmr2 pdr3 pcr3 v ss pdr3: pcr3: pmr2: pucr3: port data register 3 port control register 3 port mode register 2 port pull-up control register 3 figure b.1(b) port 3 block diagram (pin p35) p3 n pdr3 pucr3 pcr3 internal data bus v ss pucr3: pdr3: pcr3: n = 4 or 3 port pull-up control register 3 port data register 3 port control register 3 v cc v cc figure b.1(c) port 3 block diagram (pins p34 and p33)
rev. 4.00, 03/04, page 435 of 462 p3 n v cc v cc pucr3 pmr3 internal data bus pdr3 pcr3 v ss pdr3: pcr3: pmr3: pucr3: n = 2 or 1 port data register 3 port control register 3 port mode register 3 port pull-up control register 3 tmofh (p3 2 ) tmofl (p3 1 ) figure b.1(d) port 3 block diagram (pins p32 and p31) b.2 port 4 block diagrams p4 3 pmr2 internal data bus pmr2: port mode register 2 figure b.2(a) port 4 block diagram (pin p43)
rev. 4.00, 03/04, page 436 of 462 p42 pdr4 pcr4 v ss pdr4: pcr4: port data register 4 port control register 4 v cc scinv3 txd32 sci3 module internal data bus spc32 figure b.2(b) port 4 block diagram (pin p42)
rev. 4.00, 03/04, page 437 of 462 p41 v cc sci3 module pdr4 internal data bus pcr4 v ss pdr4: pcr4: port data register 4 port control register 4 re32 rxd32 scinv2 figure b.2(c) port 4 block diagram (pin p41)
rev. 4.00, 03/04, page 438 of 462 p40 v cc sci3 module pdr4 pcr4 v ss pdr4: pcr4: port data register 4 port control register 4 sckie32 sckoe32 scko32 scki32 internal data bus figure b.2(d) port 4 block diagram (pin p40)
rev. 4.00, 03/04, page 439 of 462 b.3 port 5 block diagram p5 n v cc v cc pucr5 internal data bus pmr5 pdr5 pcr5 v ss pdr5: pcr5: pmr5: pucr5: n = 7 to 0 port data register 5 port control register 5 port mode register 5 port pull-up control register 5 figure b.3 port 5 block diagram
rev. 4.00, 03/04, page 440 of 462 b.4 port 6 block diagram p6 n v cc v cc pucr6 pdr6 pcr6 internal data bus v ss pdr6: pcr6: pucr6: n = 7 to 0 port data register 6 port control register 6 port pull-up control register 6 figure b.4 port 6 block diagram
rev. 4.00, 03/04, page 441 of 462 b.5 port 7 block diagram p7 n v cc pdr7 pcr7 internal data bus v ss pdr7: pcr7: n = 7 to 0 port data register 7 port control register 7 figure b.5 port 7 block diagram
rev. 4.00, 03/04, page 442 of 462 b.6 port 8 block diagram p8 0 v cc pdr8 pcr8 internal data bus v ss pdr8: pcr8: port data register 8 port control register 8 figure b.6 port 8 block diagram (pin p80) b.7 port 9 block diagrams p9 n pdr9 pmr9 internal data bus v ss pmr9: pdr9: n = 1 or 0 port mode register 9 port data register 9 pwm module pwmn + 1 figure b.7(a) port 9 block diagram (pins p91 and p90)
rev. 4.00, 03/04, page 443 of 462 p9 n pdr9 internal data bus v ss pdr9: n = 5 to 2 port data register 9 figure b.7(b) port 9 block diagram (pins p95 to p92) b.8 port a block diagram pa n v cc pdra pcra internal data bus v ss pdra: pcra: n = 3 to 0 port data register a port control register a figure b.8 port a block diagram
rev. 4.00, 03/04, page 444 of 462 b.9 port b block diagram pb n dec internal data bus a/d module amr3 to amr0 v in n = 3 to 0 figure b.9 port b block diagram
rev. 4.00, 03/04, page 445 of 462 appendix c port states in each operating state table c.1 port states port reset sleep subsleep standby watch subactive active p37top31 high impedance retained retained high impedance * retained functioning functioning p43top40 high impedance retained retained high impedance retained functioning functioning p57top50 high impedance retained retained high impedance * retained functioning functioning p67top60 high impedance retained retained high impedance * retained functioning functioning p77top70 high impedance retained retained high impedance retained functioning functioning p80 high impedance retained retained high impedance retained functioning functioning p95top90 high impedance retained retained high impedance retained functioning functioning pa3 to pa0 high impedance retained retained high impedance retained functioning functioning pb3 to pb0 high impedance high impedance high impedance high impedance high impedance high impedance high impedance note: * high level output when the pull-up mos is in on state.
rev. 4.00, 03/04, page 446 of 462 appendix d product code lineup table d.1 product code lineup of h8/3802 group product type product code model marking package (package code) hd6473802h hd6473802h 64-pin qfp (fp-64a) hd6473802fp hd6473802fp 64-pin lqfp (fp-64e) regular product hd6473802p hd6473802p 64-pin dilp (dp-64s) hd6473802d hd6473802h 64-pin qfp (fp-64a) hd6473802fpi hd6473802fp 64-pin lqfp (fp-64e) prom version product with wide-range temperature specifications hd6473802q hd6473802p 64-pin dilp (dp-64s) hd6433802h hd6433802 ( *** ) h 64-pin qfp (fp-64a) hd6433802fp hd6433802 ( *** ) fp 64-pin lqfp (fp-64e) hd6433802p hd6433802 ( *** ) p 64-pin dilp (dp-64s) regular product hcd6433802 ? die hd6433802d hd6433802 ( *** ) h 64-pin qfp (fp-64a) hd6433802fpi hd6433802 ( *** ) fp 64-pin lqfp (fp-64e) h8/3802 mask rom version product with wide-range temperature specifications hd6433802q hd6433802 ( *** ) p 64-pin dilp (dp-64s) hd6433801h hd6433801 ( *** ) h 64-pin qfp (fp-64a) hd6433801fp hd6433801 ( *** ) fp 64-pin lqfp (fp-64e) hd6433801p hd6433801 ( *** ) p 64-pin dilp (dp-64s) regular product hcd6433801 ? die hd6433801d hd6433801 ( *** ) h 64-pin qfp (fp-64a) hd6433801fpi hd6433801 ( *** ) fp 64-pin lqfp (fp-64e) h8/3801 mask rom version product with wide-range temperature specifications hd6433801q hd6433801 ( *** ) p 64-pin dilp (dp-64s) hd6433800h hd6433800 ( *** ) h 64-pin qfp (fp-64a) hd6433800fp hd6433800 ( *** ) fp 64-pin lqfp (fp-64e) hd6433800p hd6433800 ( *** ) p 64-pin dilp (dp-64s) regular product hcd6433800 ? die hd6433800d hd6433800 ( *** ) h 64-pin qfp (fp-64a) hd6433800fpi hd6433800 ( *** ) fp 64-pin lqfp (fp-64e) h8/3800 mask rom version product with wide-range temperature specifications hd6433800q hd6433800 ( *** ) p 64-pin dilp (dp-64s) [legend] ( *** ): rom code
rev. 4.00, 03/04, page 447 of 462 table d.2 product code lineup of h8/38004 group product type product code model marking package (package code) hd64f38004h10 64f38004h10 64-pin qfp (fp-64a) hd64f38004fp10 f38004fp10 64-pin lqfp (fp-64e) regular product (2.7 v) hcd64f38004 ? die hd64f38004h4 64f38004h4 64-pin qfp (fp-64a) hd64f38004fp4 f38004fp4 64-pin lqfp (fp-64e) regular product (2.2 v) hcd64f38004c4 ? die hd64f38004h10w 64f38004h10 64-pin qfp (fp-64a) flash memory version product with wide-range temperature specifications (2.7 v) hd64f38004fp10w f38004fp10 64-pin lqfp (fp-64e) hd64338004h hd64338004h 64-pin qfp (fp-64a) hd64338004fp 38004 ( *** ) fp 64-pin lqfp (fp-64e) regular product hcd64338004 ? die hd64338004hw hd64338004h 64-pin qfp (fp-64a) h8/38004 mask rom version product with wide-range temperature specifications hd64338004fpw 38004 ( *** ) fp 64-pin lqfp (fp-64e) hd64338003h hd64338003h 64-pin qfp (fp-64a) hd64338003fp 38003 ( *** ) fp 64-pin lqfp (fp-64e) regular product hcd64338003 ? die hd64338003hw hd64338003h 64-pin qfp (fp-64a) h8/38003 mask rom version product with wide-range temperature specifications hd64338003fpw 38003 ( *** ) fp 64-pin lqfp (fp-64e) hd64f38002h10 64f38002h10 64-pin qfp (fp-64a) hd64f38002fp10 f38002fp10 64-pin lqfp (fp-64e) regular product (2.7 v) hcd64f38002 ? die hd64f38002h4 64f38002h4 64-pin qfp (fp-64a) hd64f38002fp4 f38002fp4 64-pin lqfp (fp-64e) regular product (2.2 v) hcd64f38002c4 ? die hd64f38002h10w 64f38002h10 64-pin qfp (fp-64a) h8/38002 flash memory version product with wide-range temperature specifications (2.7 v) hd64f38002fp10w f38002fp10 64-pin lqfp (fp-64e)
rev. 4.00, 03/04, page 448 of 462 product type product code model marking package (package code) hd64338002h hd64338002h 64-pin qfp (fp-64a) hd64338002fp 38002 ( *** ) fp 64-pin lqfp (fp-64e) regular product hcd64338002 ? die hd64338002hw hd64338002h 64-pin qfp (fp-64a) h8/38002 mask rom version product with wide-range temperature specifications HD64338002FPW 38002 ( *** ) fp 64-pin lqfp (fp-64e) hd64338001h hd64338001h 64-pin qfp (fp-64a) hd64338001fp 38001 ( *** ) fp 64-pin lqfp (fp-64e) regular product hcd64338001 ? die hd64338001hw hd64338001h 64-pin qfp (fp-64a) h8/38001 mask rom version product with wide-range temperature specifications hd64338001fpw 38001 ( *** ) fp 64-pin lqfp (fp-64e) hd64338000h hd64338000h 64-pin qfp (fp-64a) hd64338000fp 38000 ( *** ) fp 64-pin lqfp (fp-64e) regular product hcd64338000 ? die hd64338000hw hd64338000h 64-pin qfp (fp-64a) h8/38000 mask rom version product with wide-range temperature specifications hd64338000fpw 38000 ( *** ) fp 64-pin lqfp (fp-64e) [legend] ( *** ): rom code
rev. 4.00, 03/04, page 449 of 462 table d.3 product code lineup of h8/38104 group product type product code model marking package (package code) h8/38104 hd64f38104h f38104h 64-pin qfp (fp-64a) regular product hd64f38104fp f38104fp 64-pin lqfp (fp-64e) flash memory version hd64f38104hw f38104h 64-pin qfp (fp-64a) product with wide-range temperature specifications hd64f38104fpw f38104fp 64-pin lqfp (fp-64e) hd64338104h 38104( *** )h 64-pin qfp (fp-64a) mask rom version regular product hd64338104fp 38104( *** ) 64-pin lqfp (fp-64e) hd64338104hw 38104( *** )h 64-pin qfp (fp-64a) product with wide-range temperature specifications hd64338104fpw 38104( *** ) 64-pin lqfp (fp-64e) h8/38103 hd64338103h 38103( *** )h 64-pin qfp (fp-64a) mask rom version regular product hd64338103fp 38103( *** ) 64-pin lqfp (fp-64e) hd64338103hw 38103( *** )h 64-pin qfp (fp-64a) product with wide-range temperature specifications hd64338103fpw 38103( *** ) 64-pin lqfp (fp-64e) h8/38102 hd64f38102h f38102h 64-pin qfp (fp-64a) regular product hd64f38102fp f38102fp 64-pin lqfp (fp-64e) flash memory version hd64f38102hw f38102h 64-pin qfp (fp-64a) product with wide-range temperature specifications hd64f38102fpw f38102fp 64-pin lqfp (fp-64e) hd64338102h 38102( *** )h 64-pin qfp (fp-64a) mask rom version regular product hd64338102fp 38102( *** ) 64-pin lqfp (fp-64e) hd64338102hw 38102( *** )h 64-pin qfp (fp-64a) product with wide-range temperature specifications hd64338102fpw 38102( *** ) 64-pin lqfp (fp-64e) h8/38101 hd64338101h 38101( *** )h 64-pin qfp (fp-64a) mask rom version regular product hd64338101fp 38101( *** ) 64-pin lqfp (fp-64e) hd64338101hw 38101( *** )h 64-pin qfp (fp-64a) product with wide-range temperature specifications hd64338101fpw 38101( *** ) 64-pin lqfp (fp-64e)
rev. 4.00, 03/04, page 450 of 462 product type product code model marking package (package code) h8/38100 hd64338100h 38100( *** )h 64-pin qfp (fp-64a) mask rom version regular product hd64338100fp 38100( *** ) 64-pin lqfp (fp-64e) hd64338100hw 38100( *** )h 64-pin qfp (fp-64a) product with wide-range temperature specifications hd64338100fpw 38100( *** ) 64-pin lqfp (fp-64e) [legend] ( *** ): rom code
rev. 4.00, 03/04, page 451 of 462 appendix e package dimensions the package dimensions for the h8/38027 group, h8/38004 group, and h8/38104 group are shown in figure e.1 (fp-64a), figure e.2 (fp-64e), and figure e.3 (dp-64s). package code jedec jeita mass (reference value) fp-64a ? conforms 1.2 g * dimension including the plating thickness base material dimension 0.10 0.15 m 17.2 0.3 48 33 49 64 1 16 32 17 17.2 0.3 0.35 0.06 0.8 3.05 max 14 2.70 0? e 8? 1.6 0.8 0.3 * 0.17 0.05 0.10 +0.15 e0.10 1.0 * 0.37 0.08 0.15 0.04 unit: mm figure e.1 package dimensions (fp-64a)
rev. 4.00, 03/04, page 452 of 462 package code jedec jeita mass (reference value) fp-64e ? conforms 0.4 g * dimension including the plating thickness base material dimension m 12.0 0.2 10 48 33 116 17 32 64 49 * 0.22 0.05 0.08 0.5 12.0 0.2 0.10 1.70 max * 0.17 0.05 0.5 0.2 0 ? e 8 ? 1.0 1.45 0.10 0.10 1.25 0.20 0.04 0.15 0.04 unit: mm figure e.2 package dimensions (fp-64e)
rev. 4.00, 03/04, page 453 of 462 package code jedec jeita mass (reference value) dp-64s ? conforms 8.8 g 0.25 + 0.11 ? 0.05 0 ? ? 15 ? 1.78 0.25 0.48 0.10 0.51 min 2.54 min 5.08 max 19.05 57.6 58.5 max 1.0 1 33 32 64 17.0 18.6 max 1.46 max unit: mm figure e.3 package dimensions (dp-64s)
rev. 4.00, 03/04, page 454 of 462 appendix f chip form specifications y direction 3.73 0.05 x direction 3.60 0.05 y direction 3.73 0.25 x direction 3.60 0.25 unit: mm maximum dimensions in chip's plane 0.28 0.02 max 0.03 figure f.1 cross-sectional view of chip (hcd6433802, hcd6433801, and hcd6433800) y direction 3.27 0.05 x direction 2.73 0.05 y direction 3.27 0.25 x direction 2.73 0.25 unit: mm maximum dimensions in chip's plane 0.28 0.02 max 0.03 figure f.2 cross-sectional view of chip (hcd64338004, hcd64338003, hcd64338002, hcd64338001, and hcd64338000)
rev. 4.00, 03/04, page 455 of 462 0.28 0.02 max 0.03 y direction 3.82 0.05 x direction 4.09 0.05 y direction 3.82 0.25 x direction 4.09 0.25 unit: mm maximum dimensions in chip's plane figure f.3 cross-sectional view of chip (hcd64f38004 and hcd64f38002)
rev. 4.00, 03/04, page 456 of 462 appendix g bonding pad form 72 figure g.1 bonding pad form (hcd6433802, hcd6433801, hcd6433800, hcd64338004, hcd64338003, hcd64338002, hcd64338001, hcd64338000, hcd64f38004, and hcd64f38002)
rev. 4.00, 03/04, page 457 of 462 appendix h chip tray specifications 51 chip orientation chip tray code manufactured by dainippon ink and chemicals, incorporated product code: ct065 characteristic engraving: tct4040-060 product name chip 51 3.60 3.73 4.9 0.1 cross-sectional view: x to x' 4.0 0.05 4.0 0.05 0.6 0.1 1.8 0.1 5.9 0.1 unit: mm xx' 4.9 0.1 5.9 0.1 4.0 0.1 figure h.1 chip tray specifications (hcd6433802, hcd6433801, and hcd6433800)
rev. 4.00, 03/04, page 458 of 462 51 51 2.73 3.27 4.48 0.1 3.6 0.05 3.6 0.05 0.6 0.1 1.8 0.1 5.34 0.1 xx' 4.48 0.1 5.34 0.1 4.0 0.1 chip orientation chip tray code manufactured by dainippon ink and chemicals, incorporated product code: ct022 characteristic engraving: tct036036-060 product name chip cross-sectional view: x to x' unit: mm figure h.2 chip tray specifications (hcd64338004, hcd64338003, hcd64338002, hcd64338001, and hcd64338000)
rev. 4.00, 03/04, page 459 of 462 51 51 4.09 3.82 6.2 0.1 4.5 0.05 4.5 0.05 0.6 0.1 1.8 0.1 6.9 0.1 xx' 6.2 0.1 6.9 0.15 4.0 0.1 chip orientation chip tray code manufactured by dainippon ink and chemicals, incorporated product code: ct015 characteristic engraving: tct45-060p product name chip cross-sectional view: x to x' unit: mm figure h.3 chip tray specifications (hcd64f38004 and hcd64f38002)
rev. 4.00, 03/04, page 460 of 462
rev. 4.00, 03/04, page 461 of 462 index 10-bit pwm ............................................ 287 a/d converter ......................................... 293 clock pulse generators prescaler s ............................................ 95 prescaler w........................................... 95 subclock generator ............................... 93 system clock generator......................... 90 exception handling ................................... 69 reset exception handling ...................... 78 stack status ........................................... 81 flash memory ......................................... 129 auto-erase mode ................................. 154 auto-program mode............................ 152 boot mode........................................... 136 boot program ...................................... 136 erase/erase-verify ............................... 144 erasing units ....................................... 131 error protection................................... 146 hardware protection ........................... 146 memory read mode............................. 150 on-board programming modes ........... 136 power-down state................................ 159 program/program-verify ..................... 141 programmer mode............................... 147 programming units.............................. 131 socket adapter..................................... 147 software protection............................. 146 status polling ...................................... 157 status read mode................................. 156 interrupt internal interrupts.................................. 79 interrupt response time ......................... 81 irq interrupts ....................................... 78 wkp interrupts ..................................... 78 interrupt mask bit (i) .................................34 lcd controller/driver .............................305 lcd display ........................................314 lcd ram...........................................315 package .......................................................3 pin arrangement ..........................................7 power-down modes.................................101 module standby function.....................117 sleep mode..........................................110 standby mode......................................111 subactive mode ...................................112 subsleep mode ....................................112 register adrr ......................... 295, 339, 342, 345 adsr.......................... 296, 339, 342, 345 aegsr ....................... 223, 338, 341, 344 amr ........................... 296, 339, 342, 345 brr............................. 250, 338, 341, 344 ckstpr1 ................... 105, 340, 343, 346 ckstpr2 ................... 105, 340, 343, 346 ebr............................. 134, 338, 341, 344 eccr .......................... 224, 338, 341, 344 eccsr........................ 225, 338, 341, 344 ecpwcr .................... 221, 338, 341, 344 ecpwdr.................... 222, 338, 341, 344 fenr .......................... 135, 338, 341, 344 flmcr1 ..................... 133, 338, 341, 344 flmcr2 ..................... 134, 338, 341, 344 flpwcr..................... 135, 338, 341, 344 iegr ............................. 72, 340, 343, 346 ienr ............................. 73, 340, 343, 346 irr................................ 75, 340, 343, 346 iwpr ............................ 77, 340, 343, 346 lcr............................. 311, 339, 342, 345 lcr2........................... 313, 339, 342, 345
rev. 4.00, 03/04, page 462 of 462 lpcr .......................... 309, 339, 342, 345 ocr ............................ 205, 339, 342, 345 pcr3........................... 166, 340, 343, 346 pcr4........................... 173, 340, 343, 346 pcr5........................... 177, 340, 343, 346 pcr6........................... 181, 340, 343, 346 pcr7........................... 185, 340, 343, 346 pcr8........................... 187, 340, 343, 346 pcra.......................... 191, 340, 343, 346 pdr3 .......................... 166, 339, 342, 345 pdr4 .......................... 172, 339, 342, 345 pdr5 .......................... 177, 339, 342, 345 pdr6 .......................... 181, 339, 342, 345 pdr7 .......................... 184, 339, 342, 345 pdr8 .......................... 187, 340, 342, 345 pdr9 .......................... 188, 340, 342, 345 pdra.......................... 190, 340, 342, 345 pdrb.......................... 193, 340, 342, 345 pmr2.......................... 169, 339, 342, 345 pmr3.......................... 168, 339, 342, 345 pmr5.......................... 178, 339, 342, 345 pmr9.......................... 189, 340, 343, 346 pmrb ......................... 193, 340, 343, 346 pucr3........................ 167, 340, 342, 345 pucr5........................ 178, 340, 343, 346 pucr6........................ 182, 340, 343, 346 pwcr......................... 289, 339, 342, 345 pwdr......................... 290, 339, 342, 345 rdr ............................ 243, 339, 341, 344 rsr..................................................... 243 scr3........................... 246, 338, 341, 344 smr............................ 244, 338, 341, 344 spcr .......................... 173, 338, 341, 344 ssr ............................. 248, 338, 341, 344 syscr1...................... 102, 340, 343, 346 syscr2...................... 104, 340, 343, 346 tca ............................ 201, 339, 341, 344 tcr............................. 206, 339, 342, 345 tcsr .......................... 207, 339, 342, 345 tcsrw....................... 235, 339, 341, 344 tcw ........................... 237, 339, 341, 344 tdr ............................ 244, 338, 341, 344 tma............................ 200, 339, 341, 344 tsr ..................................................... 244 wegr........................... 77, 338, 341, 344 serial communication interface 3 (sci3) 241 asynchronous mode............................ 256 bit rate................................................. 250 break................................................... 282 clocked synchronous mode ................ 268 framing error ...................................... 264 mark state............................................ 282 multiprocessor communication function ........................................................ 274 overrun error ...................................... 264 parity error .......................................... 264 timer a................................................... 199 timer f ................................................... 203 16-bit timer mode................................ 211 8-bit timer mode.................................. 212 vector address........................................... 71 watchdog timer....................................... 234
renesas 8-bit single-chip microcomputer hardware manual h8/3802, h8/38004, h8/38104 group publication date: 1st edition, november, 1999 rev.4.00, march 16, 2004 published by: sales strategic planning div. renesas technology corp. edited by: technical documentation & information department renesas kodaira semiconductor co., ltd. ? 2004. renesas technology corp., all rights reserved. printed in japan.
colophon 1.0 sales strategic planning div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan http://www.renesas.com renesas technology america, inc. 450 holger way, san jose, ca 95134-1368, u.s.a tel: <1> (408) 382-7500 fax: <1> (408) 382-7501 renesas technology europe limited. dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, united kingdom tel: <44> (1628) 585 100, fax: <44> (1628) 585 900 renesas technology europe gmbh dornacher str. 3, d-85622 feldkirchen, germany tel: <49> (89) 380 70 0, fax: <49> (89) 929 30 11 renesas technology hong kong ltd. 7/f., north tower, world finance centre, harbour city, canton road, hong kong tel: <852> 2265-6688, fax: <852> 2375-6836 renesas technology taiwan co., ltd. fl 10, #99, fu-hsing n. rd., taipei, taiwan tel: <886> (2) 2715-2888, fax: <886> (2) 2713-2999 renesas technology (shanghai) co., ltd. 26/f., ruijin building, no.205 maoming road (s), shanghai 200020, china tel: <86> (21) 6472-1001, fax: <86> (21) 6415-2952 renesas technology singapore pte. ltd. 1, harbour front avenue, #06-10, keppel bay tower, singapore 098632 tel: <65> 6213-0200, fax: <65> 6278-8001 renesas sales offices
h8/3802, h8/38004, h8/38104 group

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